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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • SystemVerilog Constrained Random Verification - August 18th
      • Formal Verification Part 1 - August 20th
      • UVM Transactions - August 26th
      • Formal Verification Part 2 - September 1st
      • ISO 26262 in Simple Terms - September 3rd
      • ISO 26262 Requirements Management - September 17th
      • ISO 26262 Bottoms-Up Safety Analysis - September 29th
      • Events Calendar

    • On Demand Seminars

      • Improving Your SystemVerilog Language and UVM Methodology Skills
      • Visualizer Debug Environment
      • What’s New in Functional Verification from Mentor - Spring 2020
      • All On-Demand Seminars

    • Recording Archive

      • DVCon 2020 - Featured Presentations
      • DAC 2019 Session Recordings
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
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    • Verification Horizons Publication

      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Verification Horizons - December 2019
      • Issue Archive

    • About Us

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      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
  • Home /
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  • What’s New in Functional Verification from Mentor - Spring 2020

What’s New in Functional Verification from Mentor - Spring 2020

Just like time and the tides, the complexity of electronic systems, and the need to verify that they will function correctly, wait for no one. Without a comprehensive suite of verification tools that evolves to fit the needs of this inexorable growth, it would quickly become impossible for you to do your job. This 5-hour series of short product-focused webinars will show you how Mentor’s suite of Functional Verification tools continues to deliver productivity enhancements in all aspects verification to keep you ahead of the curve.

Functional Verification has always been a multifaceted problem, requiring different tools to address different aspects of the problem. The key to productivity is a unified suite of tools with complementary capabilities to make it easier and quicker for you to apply the latest technologies to get your verification job done. This web seminar series will provide a comprehensive overview of Mentor’s Functional Verification tools and show how each tool has been optimized to find bugs as early in the verification process as possible.

Tom Fitzpatrick
Gordon Allan
Vijay Chobisa
Rich Edelman
Munish Goyal
Matthew Ballance
Joe Hupcey
Mark Eslinger
Chris Giles
Jacob Wiltgen
Acceleration Clock-Domain Crossing Debug Formal-Based Techniques Functional Safety Portable Test and Stimulus Simulation-Based Techniques Verification IP
Crawl

Sessions

Optimizing Time to Bug

Optimizing Time to Bug Session | Subject Matter Expert - Tom Fitzpatrick | What’s New in Functional Verification from Mentor Web Seminar

A “keynote” presentation for the series, highlighting the issues that have cropped up in recent years, including the explosion in the amount of data that must new be verified and managed and the safety and security of the data and systems they control.

Productivity in the Questa Simulation Flow

Productivity in the Questa Simulation Flow Session | Subject Matter Expert - Gordon Allan | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn every step of the Questa Simulation-based verification flow has been optimized and accelerated, from regression management, to incremental compilation and elaboration, to debug and coverage.

Market-Driven Trends in Hardware Emulation

Market-Driven Trends in Hardware Emulation Session | Subject Matter Expert - Vijay Chobisa | What’s New in Functional Verification from Mentor Web Seminar

In this session you will learn how AI/ML, 5G, networking and ADAS designs are affecting verification and validation and how Veloce Strato & VirtuaLAB address these verification challenges.

Context-Aware Debug for Complex Heterogeneous Environments

Context-Aware Debug for Complex Heterogeneous Environments Session | Subject Matter Expert - Rich Edelman | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how to utilize Visualizer to tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …).

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP Session | Subject Matter Expert - Munish Goyal | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how Questa Verification IP is architected for ease of use and how the library gives you everything you need to verify standard protocols in your UVM environment.

Find Bugs Earlier with Strategy-Guided Stimulus

Find Bugs Earlier with Strategy-Guided Stimulus Session | Subject Matter Expert - Matthew Ballance | What’s New in Functional Verification from Mentor Web Seminar

In this session, we will discuss the benefits of focusing on random-regressions and coverage-closure phases of the verification cycle, and see how strategy-guided stimulus helps to accomplish this.

Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal

Automated Formal-Based Apps - Improving Quality and Time-to-Market with Formal Session | Subject Matter Expert - Joe Hupcey | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how formal apps can help you address high-value verification challenges; finding deep bugs in complex logic, accelerating code coverage closure, validating low power clock gating and more.

Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal

Direct Formal Property Checking - Improving Quality and Time-to-Market with Formal Session | Subject Matter Expert - Mark Eslinger | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn how formal analysis works, and you can create an effective "formal testbench" with very basic, easy-to-write properties.

Confronting Inevitability: Finding Clock and Reset Issues Before They Find You

Confronting Inevitability: Finding Clock and Reset Issues Before They Find You Session | Subject Matter Expert - Chris Giles | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn the full scope of synchronization issues and how Questa’s clock- and reset-domain crossing solution will help you avoid costly design flaws and accelerate your time to market.

Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance

Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance Session | Subject Matter Expert - Jacob Wiltgen | What’s New in Functional Verification from Mentor Web Seminar

In this session, you will learn about a powerful combination of Mentor’s functional verification and functional safety products together with Siemens’ lifecycle management tools provide built-in guidance and automation helping you navigate the difficult waters of safety compliance.

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