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  3. Debug

Advanced Debug Techniques

In this track, you will learn how the Visualizer Debug Environment can debug and verify your complex SoCs and FPGAs.

  • Debug

Rich Edelman Jason Polychronopoulos Athira Panicker Tomasz Piekarz

Last Updated May 2022
  • Debug
Begin Track

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  • Advanced Debug Techniques
  • 1. Prevent Performance Problems with Prompt RTL Profiling
  • 2. Accelerate Development Using Advanced Debugging Approaches
  • 3. I Didn’t Know Visualizer Could Do That
  • 4. Better UVM Debug with Visualizer
  • 5. Introduction to Visualizer for the Verilog Users
  • 6. Introduction to Visualizer for the VHDL Users
  • 7. Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer
  • 8. Visualizer Coverage: Debug and Visualize All Your Coverage
  • 9. Embedded Software Debug Using Codelink and Visualizer
  • 10. Verification and Debug: Old School Meets New School
  • 11. Functional Debug: Verification and Beyond
  • 12. Transaction Recording & Debug with Questa & Visualizer
  • 13. Productive Low Power Debug Across All Engines and Flows
  • 14. Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?
  • 15. Enterprise Debug for Simulation
  • 16. Evolution of Debug
  • Sessions

    • Prevent Performance Problems with Prompt RTL Profiling

      Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.

      Track Nov 09, 2023 by Rich Edelman

      • Debug

    • Accelerate Development Using Advanced Debugging Approaches

      In this session, you will learn how Visualizer Debug Environment provides a high-performance, high-capacity, tightly integrated debug environment for Simulation and Emulation.

      Track May 10, 2022 by Rich Edelman

      • Debug

    • I Didn’t Know Visualizer Could Do That

      In this session, you will learn about Visualizer's powerful features that improve debug productivity for System Verilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

      Track Mar 30, 2021 by Rich Edelman

      • Debug

    • Better UVM Debug with Visualizer

      In this session you will learn UVM Debug tips and tricks in both Post simulation and Live simulation.

      Track Jun 02, 2020 by Rich Edelman

      • Debug

    • Introduction to Visualizer for the Verilog Users

      This session will introduce the Visualizer Debug Environment for Verilog and UVM.

      Track Jun 16, 2020 by Rich Edelman

      • Debug

    • Introduction to Visualizer for the VHDL Users

      This session will introduce the Visualizer Debug Environment for VHDL and UVM.

      Track Jun 30, 2020 by Rich Edelman

      • Debug

    • Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

      This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.

      Track Oct 27, 2020 by Jason Polychronopoulos

      • Debug

    • Visualizer Coverage: Debug and Visualize All Your Coverage

      In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.

      Track Nov 19, 2020 by Athira Panicker

      • Debug

    • Embedded Software Debug Using Codelink and Visualizer

      In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.

      Track Dec 08, 2020 by Tomasz Piekarz

      • Debug

    • Verification and Debug: Old School Meets New School

      You will learn how to use the best of old and new school debug techniques to find problems faster and to better answer “am I done yet”.

      Track Oct 15, 2014 by Rich Edelman

      • Debug

    • Functional Debug: Verification and Beyond

      In this session, we will discuss the features of functional debug solutions and the benefits they bring throughout the SoC development process.

      Track Mar 31, 2021 by Hanan Moller

      • Debug

    • Transaction Recording & Debug with Questa & Visualizer

      This session will explore the Transaction Recording (TR) and debug capabilities of Questa Sim and how they can be applied in the context of a UVM testbench.

      Track Jun 20, 2019 by Rich Edelman

      • Debug

    • Productive Low Power Debug Across All Engines and Flows

      In this session, we will answer the top nine questions asked for debugging low power in your design.

      Track Jan 28, 2019 by Gordon Allan

      • Debug

    • Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

      This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.

      Track Dec 12, 2017 by Neil Bulman

      • Debug

    • Enterprise Debug for Simulation

      In this session, you will learn more about common debug challenges and modern debug solutions.

      Track Nov 11, 2016 by Moses Satyasekaran

      • Debug

    • Evolution of Debug

      In this session, Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.

      Track Aug 25, 2015 by Gordon Allan

      • Debug

  • Overview

    Complex testing and methodology with complex silicon requires powerful but simple to use debug solutions. Debug Expert, Rich Edelman will explore better UVM debugging, debug for Verilog and debug for VHDL including automation for driver tracing and X-tracing, post-simulation and live-simulation debug, class based debug and transaction debug.

    The Visualizer Debug Environment is a powerful framework for debug and verification for simulation, emulation, formal, CDC, lint, analog and other technologies. Assertion debug and coverage analysis are available, along with traditional waveform debug, source code debug with the capacity and performance for even large gate-level designs.

    In these sessions you will learn how the Visualizer Debug Environment can debug and verify your complex SoCs and FPGAs.

  • Forum Discussion - Debug

    • Randomize always the same number with $urandom_range

      Jan 10, 2016 SystemVerilog
    • Issue with $fwrite string truncation

      gbonneau Apr 26, 2025 SystemVerilog
    • UVMC command API and config db

      Amal Apr 25, 2025 UVM
    • Uvm_phase

      Jul 03, 2015 UVM
    • Multiclock assertion

      Apr 10, 2025 SystemVerilog
    • How to close the print info,just like "[RegModel] Read register via user backdoor...",when i set "+UVM_VERBOSITY=UVM_HIGH"?

      Apr 15, 2025 UVM
    • Why we are not raising and dropping objection in driver run_phase?

      Mar 30, 2025 UVM
    • Latch causing simulation perf issues

      Mar 28, 2025 SystemVerilog
    • Timescale versus UVM info?

      julien_payen Mar 26, 2025 UVM
    • Streaming operator

      Mar 24, 2025 SystemVerilog
    Join the Debug Discussion
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