Session Title | Abstract | Slides |
Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow - Walter Gude | Applications Engineer Consultant |
In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution. | PDF ![]() |
Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform - Moses Satyasekaran | Director, Simulation Product Line |
During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities. | PDF ![]() |
Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data - Austin Mam | Applications Engineer |
This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity, inspired by the collective feedback gathered from verification teams over many years. | PDF ![]() |
The New Leader in Verification IP: Questa + Avery Solutions - Gordon Allan | Product Manager, Verification IP |
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the industry leader for Verification IP. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications. | PDF ![]() |
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