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Protocol Layering in UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
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Introduction to UVM Registers
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.
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C-Based Stimulus for UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn more about a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents.
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UVM Debug
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this Verification Cookbook session, you will learn how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.
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UVM Scoreboarding and Results Prediction
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.
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OVM to UVM Migration
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session you will be introduced to a step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.
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Customization in UVM
Webinar - Sep 17, 2012 by Tom Fitzpatrick
In this session, you will learn how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT and how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.
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Improving FPGA Debugging with Assertions
Article - Sep 10, 2012 by Harry Foster
Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.
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UVM Connect 2.2 Kit
Resource (Tarball) - Sep 07, 2012 by John Stickley
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Improve AMS Verification Performance
Track - Sep 01, 2012 by Ahmed Eisawy
This track will introduce various modeling practices available in an Analog/Mixed-Signal (AMS) design environment to help understand how to efficiently utilize them. Understanding the modeling tools available in AMS domain, will help learn how to properly address them, thus, help improve the AMS verification performance.
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Overview to Improve AMS Performance
Session - Sep 01, 2012 by Ahmed Eisawy
This session introduces the challenges in mixed-signal verification performance. A high-level description of the accuracy vs. performance/capacity tradeoffs is also provided along with the various available technologies that attempt to address the different areas of tradeoffs.
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AMS Engines
Session - Sep 01, 2012 by Ahmed Eisawy
This session covers the 2 main simulator technologies used in mixed-signal verification: AMS Simulation and Analog/Digital Co-Simulation. In each case, the technology is presented along with its merits and demerits. Additionally, capabilities expected from AMS engines are presented.
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Modeling Abstraction
Session - Sep 01, 2012 by Ahmed Eisawy
This session defines the language choices available in a mixed-signal design structure and how each choice impacts the performance and quality of the results. Then, introduces the concept of abstraction which helps define only a subset of effects that are of interest to each design phase. Abstraction helps the mixed-signal verification performance which directly helps improve the quality of the design by allowing the designer to cover/test more behaviors of the design.
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AMS Modeling Guidance
Session - Sep 01, 2012 by Ahmed Eisawy
This session attempts to offer some general guidelines in developing models for the various analog and mixed-signal domains to achieve the optimum design flow to meet the requirements with reasonable resources. The session also covers some of the "good modeling practices" and comparing them to the "bad modeling practices" oftentimes a model developer would fall into.
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Questa ADMS: AMS Performance
Session - Sep 01, 2012 by Ahmed Eisawy
This session introduces Questa ADMS, and how this tool can be adapted in existing design flows supporting the available methodologies with little or no impact on the design flow, supporting virtually all language standards with a variety of features and capabilities to help accurately and efficiently model and verify complex mixed-signal designs to reach the goal of successful first tape-out using reasonable resources.
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FPGA Verification Capabilities
Track - Aug 30, 2012 by Ray Salemi
This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
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Introduction from Harry Foster
Session - Aug 30, 2012 by Harry Foster
This session is an introduction to various code coverage metrics and how to apply them.
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Overview and Welcome
Session - Aug 30, 2012 by Ray Salemi
This session is an introduction to the seven steps for evolving your FPGA verification capabilities.
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Code Coverage
Session - Aug 30, 2012 by Ray Salemi
This session is an introduction to various code coverage metrics and how to apply them.
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Test Planning
Session - Aug 30, 2012 by Ray Salemi
This session shows how you can create a test plan that systematically captures all the functionality in your design so you can test it.
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Applied Assertions
Session - Aug 30, 2012 by Ray Salemi
This session discusses how to use assertions in a design, and then demonstrates how to insatiate an OVL checker into a VHDL design.
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Transactions
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to create a transaction level testbench using modules instead of object. You will quickly have a testbench where modules talk to each other using transactions instead of signals.
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Self-Checking Testbenches
Session - Aug 30, 2012 by Ray Salemi
This session demonstrates how to combine predictors and comparators to form a self-checking testbench.
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Automatic Stimulus
Session - Aug 30, 2012 by Ray Salemi
This session introduces constrained-random stimulus for automatic stimulus generation.
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Functional Coverage
Session - Aug 30, 2012 by Ray Salemi
This session shows you how to implement functional coverage using SystemVerilog covergroups.