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RTL Enhancements

Session - Jan 18, 2013 by Jim Lewis

VHDL 2008 enhancements simplify RTL coding. Among these changes are simplified sensitivity lists, simplified conditionals (if statements), and simplified case statements. This session examines these changes and the value they deliver.
Operator Enhancements

Session - Jan 18, 2013 by Jim Lewis

This session will discuss the value of the many new enhancements to the VHDL 2008 operators including Unary reduction, Array operations and mods for physical time.
Package Type Enhancements

Session - Jan 18, 2013 by Jim Lewis

VHDL 2008 includes numerous tune ups to the packages and how the packages are integrated into the language. The session explores the new packages and modifications to the packages as well as the value these updates deliver.
Fixed Point Package

Session - Jan 18, 2013 by Jim Lewis

The new package, fixed_generic_pkg, defines fixed point math types and operations. This session will explain the details of the new package.
Floating Point Package

Session - Jan 18, 2013 by Jim Lewis

The new package, float_generic_pkg, defines floating point math types and operations. This session will explain the details of the new package.
VHDL 2008: Why It Matters

Track - Jan 17, 2013 by Jim Lewis

VHDL 2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed- and floating-point math packages. VHDL 2008 is the largest change to VHDL since 1993; this track is designed to explain the value of the new VHDL 2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.
Improve AMS Verification Quality

Track - Dec 01, 2012 by Ahmed Eisawy

This track introduces methodologies available in AMS design environments that could help quantify the quality of the Analog/Mixed-Signal (AMS) verification process. Understanding these approaches, will help learn how to properly address the various issues and problems in AMS verification process, thus, help improve the overall process Quality.
Overview to Improve AMS Quality

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces the challenges in improving mixed-signal verification quality. A high-level description of the various aspects affecting the overall quality of a mixed-signal design is introduced.
Analog Aspects in AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session covers the main aspects that affect the quality of an analog design and introduces the possible means to address those areas efficiently to help improve the quality of an analog design, while being integrated in the overall AMS design.
Extend Power Aware Verification to AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces the concept of power aware verification, why it’s needed in a Digital domain and how it can be used in an AMS design. Mixed-signal power aware verification is further described to show the benefits from such flow to the overall quality of AMS design and verification.
Extend Structured Formal Verification to AMS

Session - Dec 01, 2012 by Ahmed Eisawy

This session defines the necessary extensions to the digital structured formal verification to the mixed-signal environment. Extending the structured formal verification to the mixed-signal domain is about covering how to write mixed-signal properties to the same database used in the digital domain for proper coverage management and thus, improve the overall quality.
Questa ADMS: AMS Quality

Session - Dec 01, 2012 by Ahmed Eisawy

This session introduces Questa ADMS, and how it can be adapted in existing design flows supporting available methodologies with little or no impact on the design flow, supporting virtually all language standards with a variety of features and capabilities to help improve the overall quality of a mixed-signal design and verification to reach the goal of successful first tape-out using reasonable resources.
Effectively Modeling and Analyzing Coverage

Webinar - Nov 15, 2012 by Tom Fitzpatrick

In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.
UART Reference

Resource (Reference Documentation) - Oct 09, 2012 by Verification Methodology Team

The Siemens EDA UART is a soft design IP core. It has been designed to be generally compatible with the industry standard 16550A UART, but there are a small number of differences.
ST-Ericsson Speeds Time to Functional Verification Closure with Questa

Article - Oct 01, 2012 by Rachida El IDRISSI - ST-Ericsson

Functional verification is one of the most critical steps in the IC development cycle. As complexity increases, along with the associated cost of fixing late-stage functional defects, manufacturers including ST-Ericsson are putting additional effort into the up-front verification process.
The Top Five Formal Verification Applications

Article - Oct 01, 2012 by Roger Sabbagh - Siemens EDA

It's no secret. Silicon development teams are increasingly adopting formal verification to complement their verification flow in key areas. Formal verification statically analyzes a design's behavior with respect to a given set of properties.
Three Steps to Unified SoC Design and Verification

Article - Oct 01, 2012 by Mark Peryer

Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.
Evolution of UPF: Getting Better All the Time

Article - Oct 01, 2012 by Erich Marschner

This article gives a high-level overview of the concepts and capabilities that UPF provides and how those concepts and capabilities have evolved over the past few years. It also gives a preview of what is coming in the next version of UPF.
Improving Analog/Mixed-Signal Verification Productivity

Article - Oct 01, 2012 by Ahmed Eisawy

Nearly all of today's chips contain Analog/Mixed-Signal circuits. Although these often constitute only 25% of the total die, they may be 100% of the product differentiation and also, unfortunately, 80% of the problems in actually getting the chip to market in a cost effective and timely way.
VHDL-2008: Why It Matters

Article - Oct 01, 2012 by Jim Lewis

This article overviews the changes and the value they bring to your design process. Topics are categorized into three major sections: testbench, RTL, and packages/operators.
Verification Horizons - Volume 8, Issue 3

Resource (Verification Horizons Archive) - Oct 01, 2012 by Tom Fitzpatrick

"For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible.”
UVM 1.1c Class Reference

Resource (Reference Documentation) - Sep 19, 2012 by

v1.1c The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
More About UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to implement registers and score-boarding at the register layer.
Protocol Layering in UVM

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.
Introduction to UVM Registers

Webinar - Sep 17, 2012 by Tom Fitzpatrick

In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.