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UVM 2017-1.0 Reference Implementation

Resource (Tarball) - Aug 29, 2018 by
UPF Information Model: The Future of Low-Power Verification Today

Paper - Aug 28, 2018 by Progyna Khondkar

The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.
UPF Information Model - The Future of Low-Power Verification Today

Resource (Paper (.PDF)) - Aug 28, 2018 by Progyna Khondkar

The IEEE 1801-2015 or UPF 3.0 language reference manual (LRM) introduces a new conceptual low power verification methodology, known as ‘UPF information model’. The model captures power management information from UPF commands and their semantics applied on designs (generally specified in different HDL e.g. Verilog, SystemVerilog, VHDL etc.). The UPF commands are power intents applied on a design, intended to leverage low power.
Using Automation to Close the Loop Between Functional Requirements and their Verification

Webinar - Aug 10, 2018 by Brian Craw

This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item. The final pieces needed to close the loop is the proof that the coverage item was met in a passing simulation.
Using Automation to Close the Loop Between Functional Requirements and their Verification

Resource (Slides (.PDF)) - Aug 10, 2018 by Brian Craw

This session will define a “Verified by” relationship between the Verification Requirement and the Coverage Intent work item and the Verification Requirement and Test work item.
Power Aware Simplifies Parametric PA-SIM Regression

Resource (Slides (.PDF)) - Aug 02, 2018 by
Portable Stimulus versus UVM: What's the Difference?

Resource (Slides (.PDF)) - Jul 30, 2018 by John Aynsley

We compare the Accellera Portable Test and Stimulus Standard (PSS) with the Universal Verification Methodology (UVM), and ask exactly what the difference is between the two when it comes to generating stimulus for hardware verification and SoC verification.
Data Mining for SoC Level Performance

Resource (Slides (.PDF)) - Jul 26, 2018 by Mark Olen

This session describes how to use data mining techniques to analysis SoC level performance metrics to find problems that escape even the best simulation and emulation processes - including SoC level bandwidth, latency, cache coherency, opcode execution performance, and more.
Validating Your SoC is True to Requirements

Resource (Slides (.PDF)) - Jul 26, 2018 by Stephen Bailey
DAC 2018 Academy PDF Presentation: UVM 1800.2 & The New and Improved UVM Cookbook

Resource - Jul 26, 2018 by
Portable Stimulus: A New Hope

Resource (Slides (.PDF)) - Jul 26, 2018 by Tom Fitzpatrick

This session will provide an overview of the new Portable Stimulus Standard, show expected use models and provide some concrete examples of how to apply this exciting technology.
Building An Integrated Verification Flow

Resource (Slides (.PDF)) - Jul 26, 2018 by Neil Johnson

While a lot of information is produced to introduce and support individual verification techniques, methods for applying a variety of verification techniques in a complementary way are harder to come by. In this session, we’ll discuss the factors and decisions that go into building an effective verification flow including what techniques to use and how they can be used together.
Emulation Platform Brings Unique Solutions to Automotive Market

Resource (Slides (.PDF)) - Jul 26, 2018 by Vijay Chobisa
AMS Verification Methodology for GPUs in AI and Deep Learning Applications

Resource (Slides (.PDF)) - Jul 26, 2018 by
Portable Stimulus from IP to SoC - Achieve More Verification

Resource (Slides (.PDF)) - Jul 26, 2018 by Matthew Ballance

This session will explain the buzz about the emerging Accellera Portable Stimulus Standard and how users have long been applying Portable Stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity.
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

Resource (Recording) - Jul 26, 2018 by Kurt Takara

In this session we will share a real world case study of how the customer applied Questa CDC at the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)
Comprehensive CDC Verification with Advanced Hierarchical Data Models

Article - Jun 29, 2018 by Ping Yeung

The size and complexity of designs, and the way they are assembled, is changing the clock-domain crossing (CDC) verification landscape. It is now common for these complex SoCs to have hundreds of asynchronous clocks.
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models

Article - Jun 29, 2018 by Matthew Ballance

Writing and reading registers is the primary way that the behavior of most IPs is controlled and queried. As a consequence of how fundamental registers are to the correct operation of designs, register tests are a seemingly-simple but important aspect of design verification and bring-up. At IP level, the correct implementation of registers must be verified – that they are accessible from the interfaces on the IP block and that they have the correct reset levels.
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal

Article - Jun 29, 2018 by Doug Smith

The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing.
Coverage Driven Verification of NVMe Using Questa VIP (QVIP)

Article - Jun 29, 2018 by Anurag Singh - Siemens EDA

Verification planning requires identification of the key features from the design specification along with prioritization and testing of the functionality that leads to the development of a coverage model.
Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs

Article - Jun 29, 2018 by Progyna Khondkar

Part I of this article provided a consolidated approach to understand verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structures of the design.
Three Main Components to Look for in Your Emulation Platform

Article - Jun 29, 2018 by Vijay Chobisa

A significant evolution is underway in SoC verification and validation. The complexity of SoC designs has resulted in the need to perform both comprehensive verification as well as system-level validation very early in the design cycle, often before stable RTL code is available for the entire design. This same complexity has also created the need for extensive internal visibility into the design to understand subtle problems that can occur during silicon bring-up.
Complex Addressable Registers in Mission Critical Applications

Article - Jun 29, 2018 by Ishanee Bajpai - Agnisys

In this article, we will discuss some complex registers that we have seen our customers use in mission-critical applications.
RTL Glitch Verification

Article - Jun 29, 2018 by Ajay Daga - FishTail Design Automation

It is important that certain timing endpoints on a design are safe from glitches. For example, it is necessary that an asynchronous reset never have a glitch that momentarily resets a flop. It is also necessary that multi-cycle paths are safe from glitches, i.e., it should not be the case that while a cycle accurate simulation of the RTL shows correct multi-cycle behavior, once delays are accounted for a glitch can propagate along the path resulting in a single-cycle path.
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer

Article - Jun 29, 2018 by Marcela Zachariášová, Luboš Moravec - Codasip Ltd.

In this article, Codasip and Siemens EDA aim to describe their methodology of effective verification of RISC-V processors, based on a combination of standard techniques, such as UVM and emulation, and new concepts that focus on the specifics of the RISC-V verification, such as configuration layer, golden predictor model, and FlexMem approach.