UPCOMING WEBINAR

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

March 14th @ 8:00 AM US/Pacific

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  1. Introduction

    The size and complexity of designs, and the way they are assembled, is changing the clock domain crossing (CDC) verification landscape. It is now common for these complex SoCs to have hundreds of asynchronous clocks.

    As CDC signals can lead to metastability, CDC metastability issues have become one of the leading cause of design re-spins. This trend has made CDC verification an even more critical step in the design verification cycle thanbefore. Naturally, this requires more time and effort to verify CDC issues and poses multiple challenges for CDC verification at the SoC level.

    There is an urgent need to move beyond the traditional, flat CDC verification approach. Flat CDC runs on an SoC are performance intensive, time-consuming, difficult to debug, and tend to prolong the verification effort. The inefficiency of flat runs is exacerbated by a high level of redundancy in debugging as the same CDC bug may be replicated across multiple instances of the same module in the full chip.

    The increasingly common usage of third-party IP and design reuse shifts the emphasis of CDC verification. Often the IP blocks have already been verified to be free of CDC issues (i.e., they are CDC clean); thus validating the integration of IP into mega-blocks and mega-blocks into subsystems becomes more important. To handle complex designs efficiently, we also require a good methodology and mechanism to hide the internal detail of the IP while still verifying the integration comprehensively.

    As more IP is integrated together, reconvergence of CDC paths is becoming one of the most significant concerns in CDC design and verification. To avoid metastability issues, synchronization logic is used on CDC paths. This synchronization logic stops the propagation of metastability but can cause unpredictable propagation delays. As each CDC path can have a different unpredictable delay, the convergence of these CDC paths can lead to functional errors.

    In this paper, we describe the hierarchical data model (HDM), which is the backbone of the Questa® CDC hierarchical verification solution. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly reused across releases and across designs wherever the IP is reused. It can also be an performance efficient alternative to the traditional flat CDC verification flow.

    To help understand the importance and impact of the HDM-based hierarchical CDC flow, we will begin with a review of the existing hierarchical CDC verification methodologies. Then, we will present the improvements of the HDM-based hierarchical CDC flow and highlight its capability for verifying reconvergence of CDC paths on complex SoCs.