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2212 Results
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Code Generation Guidelines
Session - Sep 09, 2019 by Bob Oden
In this session, you will be given an overview of the flow used to generate a working simulation using the UVMF code generator.
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Code Generation Guidelines
Resource (Slides (.PDF)) - Sep 09, 2019 by Jonathan Craft
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Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Resource (Recording) - Aug 31, 2019 by Brucek Khailany
We will highlight two design automation research directions being pursued in the ASIC and VLSI Research group at NVIDIA: (1) An automated C++-to-layout VLSI flow that leverages HLS tools and open-source HLS-compatible C++ libraries for design productivity; and (2) Machine-learning assisted VLSI design techniques. We will also describe our experience using these tools as part of an agile hardware design flow to build for a deep neural network (DNN) inference accelerator testchip.
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Assuring the Integrity of RISC-V Cores and SoCs
Resource (Paper (.PDF)) - Aug 21, 2019 by Nicolae Tusinschi
The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SoC developers evaluating potential RISC-V need to check that their standards for design integrity are fully satisfied.
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A New Approach to Low Power Verification - Power Aware Apps
Resource (Paper (.PDF)) - Aug 21, 2019 by Madhur Bhargava
This paper demonstrates how Power Aware Apps can help in reporting, debugging and self-checking low power designs. We will also highlight how these apps will help offer an efficient way to significantly save verification effort and time.
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A New Approach to Low Power Verification: Power Aware Apps
Paper - Aug 21, 2019 by Madhur Bhargava - Siemens EDA
The effective verification of low power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low power objects and concepts is continuously evolving to address the low power challenges of today’s complex designs.
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Coverage Driven Verification of NVMe Using Questa VIP
Resource (Paper (.PDF)) - Aug 21, 2019 by
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Using HLS to Accelerate Computer Vision for Autonomous Drive
Resource (Slides (.PDF)) - Aug 20, 2019 by
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Source Code Download: Fun with UVM Sequences - Coding and Debugging
Resource - Aug 20, 2019 by
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Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models
Resource (Paper (.PDF)) - Aug 02, 2019 by Thomas Ellis
In this paper we will outline a set of guidelines for writing an unambiguous coverage model.
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Results Checking Strategies with Portable Stimulus
Resource (Paper (.PDF)) - Aug 02, 2019 by Tom Fitzpatrick
The key to results checking in Portable Stimulus is to understand that different levels of verification and validation environments have different needs when it comes to results checking. In a block-level environment, we might want detailed scoreboarding in addition to an overall per-operation pass/fail. In an SoC environment, we may only need an overall per-operation pass/fail.
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Transaction Recording: Anywhere Anytime
Resource (Paper (.PDF)) - Aug 02, 2019 by Rich Edelman
This paper will demonstrate a complete transaction recording system for both a stand-alone implementation and a UVM based implementation
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Transaction Recording: Anywhere Anytime
Paper - Aug 02, 2019 by Rich Edelman
Transaction debug can provide visibility where there previously was none. Even in the creation of the examples for this paper, transactions provided several “ah-ha” moments which explained the bug in the example code. It makes debug much faster, requiring only a small amount of work to implement. This paper will demonstrate a complete transaction recording system for both a stand-alone implementation and a UVM based implementation.
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Portable Stimulus: Is It Revolution or Evolution?
Conference - Jul 15, 2019 by Tom Fitzpatrick
Many claim the new Portable Test and Stimulus Standard. (PSS) from Accellera will ignite the next revolution in SoC and Electronic System functional verification. Revolutionary innovation seeks to adapt the world to new and better ideas; yet it can be disruptive, expensive and produce unpredicted outcomes.
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Portable Stimulus: Is It Revolution or Evolution?
Resource (Slides (.PDF)) - Jul 15, 2019 by Tom Fitzpatrick
In this session, you will learn how Reuse can be the Evolution that enables the PSS Revolution.
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An Emulation Strategy for AI and ML Designs
Conference - Jul 15, 2019 by Vijay Chobisa
The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session.
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An Emulation Strategy for AI and ML Designs
Resource (Slides (.PDF)) - Jul 15, 2019 by Vijay Chobisa
The emergence of Artificial Intelligence is the “next big thing” in the overall The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges.
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Tessent: DFT Enablement for AI Devices
Conference - Jul 15, 2019 by Geir Eide
Artificial Intelligence (AI) and other leading edge technologies are experiencing explosive growth in both the number of SoC designs as well as increased complexity. AI processors have architectural features and physical design practices that challenge all aspects of design including DFT. We will investigate some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed.
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Tessent: DFT Enablement for AI Devices
Resource (Slides (.PDF)) - Jul 15, 2019 by Geir Eide
In this session, we'll learn about some of the DFT challenges faced by AI designs and look at approaches that are currently being used. A few published methodologies and results will be reviewed
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Deep Learning Accelerator Using HLS
Resource (Slides (.PDF)) - Jul 15, 2019 by
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Streamlining Plan & Requirements Driven Verification
Resource - Jul 12, 2019 by
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Improving Verification Throughput of Today’s Complex Mixed-Signal ICs
Resource (Slides (.PDF)) - Jul 12, 2019 by
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Selecting the Most Productive SoC Design Verification Techniques
Resource (Slides (.PDF)) - Jul 12, 2019 by
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Veloce HYCON - OS-aware IP Development Solution
Resource (Slides (.PDF)) - Jul 12, 2019 by
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RISC-V Core and SoC: Compliance, Verification, Customization
Resource (Slides (.PDF)) - Jul 11, 2019 by Larry Lapides