|Author: Anurag Singh - Mentor, A Siemens Business Introduction: Verification planning requires identification of the key features from the design specification along with prioritization and testing of the functionality that leads to the development of a coverage model. Functional coverage is an integral part in verifying the completeness of an IP. The key to functional coverage is to make an exhaustive verification plan containing coverpoints and crosses which are extracted from the protocol specification. This paper explains the need for coverage-driven verification for Non-Volatile Memory Express (NVMe), and how QVIP achieves it. Why is Functional Coverage Important for NVMe: NVMe is an interface specification for PCI Express® based solid state drives focusing on low latency, scalability, and security. NVMe is a host controller interface and storage protocol that utilizes high-speed data transfer between enterprise and client systems and SSDs over a computer’s high-speed PCIe bus; i.e., it is an application layer. Key NVMe Attributes: Support for multiple namespaces. Namespaces are quantities of non-volatile memory that may be formatted into logical blocks and referenced using unique Namespace IDs (NSID)Queue mapping. For admin queues there is always 1:1 mapping between the Submission Queue and Completion Queue and for I/O queues there can be 1:1 as well as n:1 mapping; i.e., N submission queues can be associated with a particular completion queueSupport for 64K I/O queuesSR-IOV As design complexity increases debugging a bug in the design code can become quite difficult. This can be avoided by making a detailed test plan covering all possible scenarios. Achieving 100% functional coverage would ensure that the testing has been completed in accordance with the test plan. An NVMe subsytem can be comprised of multiple controllers; thereby increasing the complexity of verification as design behavior is controller specific. Therefore, coverage metrics play an important role in NVMe as coverage should come out to be the same for all the controllers. A coverage model is created for the bus traffic; i.e., NVMe transactions driven on a PCIe bus. Therefore coverage helps in finding bugs in the monitor component and helps in monitoring/testing of assertions as well. View & Download: Read the entire Coverage Driven Verification of NVMe Using Questa VIP technical paper.