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MathWorks® Integration

Session - Dec 29, 2020 by Bob Oden

In this session, you will learn how the UVMF code generator can automatically integrate blocks created using MathWorks® products. In addition, we will cover how a UVMF environment generated from MathWorks® output can be automatically used in subsystem or chip level simulations.
Part 7: IC/ASIC Design Trends

Resource (Verification Horizons Blog) - Dec 22, 2020 by Harry Foster

In this blog, I present trends related to various aspects of design to illustrate growing design complexity. One interesting observation from this year’s study is the continue increase in design projects working on designs less than 1M gates. This is due to a number of projects working on smaller sensor chips for IoT and automotive devices. This can potentially yield some interesting results in the study.
Part 6: FPGA Verification Language and Library Adoption Trends

Resource (Verification Horizons Blog) - Dec 16, 2020 by Harry Foster

In this blog, I’ll present FPGA design and verification language adoption trends. It is not uncommon for FPGA projects to use multiple languages when constructing their RTL and testbenches. This practice is often due to legacy code as well as purchased IP. Hence, you might note that the percentage adoption for some of the languages that I present sums to more than one hundred percent.
Part 5: FPGA Verification Technology Adoption Trends

Resource (Verification Horizons Blog) - Dec 09, 2020 by Harry Foster

In this blog, I present verification techniques and technologies adoption trends, as identified by the 2020 Wilson Research Group study. An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was about seven years ago in terms of pre-lab verification maturity—and it is catching up quickly.
Embedded Software Debug Using Codelink and Visualizer

Webinar - Dec 08, 2020 by Tomasz Piekarz

In this session, you will learn how you can save time and improve your embedded software debug techniques by utilizing tips and tricks in Post simulation.
Part 4: FPGA Verification Effort Trends (Continued)

Resource (Verification Horizons Blog) - Dec 02, 2020 by Harry Foster

In my previous blog I discussed verification effort trends in terms of project time spent in verification, as well as increasing headcount as indicated by the rising mean peak number of design and verification engineers working on FPGA projects. In this blog I continue the discussion of FPGA verification effort trends by looking at where engineers spend their time. Verification engineers are not the only project stakeholders involved in the verification process.
Visualizer Coverage: Debug and Visualize All Your Coverage

Webinar - Nov 19, 2020 by Athira Panicker

In this session, you will learn coverage techniques including; how to use testplan tracker in Visualizer to analyze the testplan, finding uncovered items using code and functional coverage windows and fixing them using coverage debugging mode.
Part 3: FPGA Verification Effort Trends

Resource (Verification Horizons Blog) - Nov 18, 2020 by Harry Foster

In my previous blog, I presented the findings from our new study related to how successful FPGA projects are in terms of verification effectiveness. In this blog I focus on FPGA verification effort trends. Directly asking study participants how much effort they spend in verification will not work. The reason is that it’s hard to find a paper or article on verification that doesn’t start with the phrase: “Seventy percent of a project’s effort is spent in verification…”
Part 2: FPGA Verification Effectiveness Trends

Resource (Verification Horizons Blog) - Nov 10, 2020 by Harry Foster

In this blog, I present the findings from our new study related how successful FPGA projects are in terms of verification effectiveness. IC/ASIC projects have often used the metric “number of required spins before production” as a benchmark to assess a project’s verification effectiveness. Historically, about 30% of IC/ASIC projects are able to achieve 1st silicon success, and most successful designs are productized on the 2nd silicon spin. Unfortunately, FPGA projects have no equivalent metric.
I’m Excited About Formal…My Journey From Skeptic to Believer

Resource (Slides (.PDF)) - Nov 09, 2020 by
Part 1: FPGA Design Trends

Resource (Verification Horizons Blog) - Nov 05, 2020 by Harry Foster

In this blog, I present trends related to various aspects of FPGA design to illustrate growing design complexity. The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021. The FPGA semiconductor market is valued at about $5 billion. The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4%.
Understanding and Minimizing Study Bias (2020 Study)

Resource (Verification Horizons Blog) - Oct 30, 2020 by Harry Foster

This blog is a continuation on the 2020 Wilson Research Group Functional Verification Study blog series. A big concern when architecting any type of study relates to addressing three types of bias: non-response bias, sample validity bias, and stakeholder bias. In this blog I point out where potential biases might occur in our study, and multiple techniques we adopted to minimize these biases.
ISO 26262 Fault Campaign Management

Resource (Slides (.PDF)) - Oct 29, 2020 by Jacob Wiltgen
ISO 26262: Fault Campaign Management

Session - Oct 29, 2020 by Jake Wiltgen

In this session, you will gain an understanding of the core challenges executing an ISO 26262 Fault Campaign and a methodology to ensure maximum efficiency. This session will describe the pros and cons of solutions contributing to the closure of a fault campaign. Additionally, a workflow and methodology will be defined which enables maximum efficiency in closing out the fault campaign.
Prologue: The 2020 Wilson Research Group Functional Verification Study

Resource (Verification Horizons Blog) - Oct 27, 2020 by Harry Foster

This is the first in a sequence of blogs that presents the findings from our new 2020 Wilson Research Group Functional Verification Study. Similar to my previous 2018 WRG functional verification study blog series , I plan to separate the discussion by FPGA and IC/ASIC findings. Study Overview The study results presented in this blog series are a continuation of a series of industry studies on functional verification that began in 2007 and continued biennially starting in 2010 through 2020.
Interactive Debug Techniques for UVM, SystemVerilog and RTL using Visualizer

Webinar - Oct 27, 2020 by Jason Polychronopoulos

Debug is one of the most time-consuming tasks verification engineers face in the design and verification of FPGAs, IPs and SoCs. Visualizer provides an advanced debug environment that includes many tools to help with both post-simulation and live-simulation debug. This session will cover different techniques for debugging SystemVerilog UVM testbench and RTL source code while running a live simulation.
Quantifying FPGA Verification Effectiveness

Article - Oct 26, 2020 by Harry Foster

The 2019 global semiconductor market was valued at $385.4 billion after experiencing a 15% decline due to a 32% drop in the memory IC market, which is expected to recover in 2021 [1] . The FPGA portion of the semiconductor market is valued at about $5 billion [2] . The FPGA semiconductor market is expected to reach a value of $7.5 billion by 2030, growing at a compounded annual growth rate (CAGR) of 4.4% during this forecast period.
Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs

Article - Oct 26, 2020 by Vikas Sharma - Siemens EDA

This article describes the verification process of the ARASAN MIPI® CSI-2-RX IP core using Questa Verification IPs.
Memory Softmodels - The Foundation of Validation Accuracy

Article - Oct 26, 2020 by Ridham Kothari - Siemens EDA

As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.
Increasing Functional Coverage by Automation for Zetta-Hz High Speed CDMA Transceiver

Article - Oct 26, 2020 by Karthik Bandaru, Priyanka Gharat, and Sastry Puranapanda - Silicon Interfaces®

The efforts to apply constrained randomization to create test cases is based on the developer or verification engineer’s perception of what test vectors are required and can easily lead to hidden bugs being overlooked. Traditionally, the coverage goals would have been reached by writing more test cases with unpredictable schedules, often impacting time-to-market goals. Functional coverage defines critical states and constrained randomization tests those states in unpredictable ways.
Unified Approach to Verify Complex FSM

Article - Oct 26, 2020 by Milan Patel - eInfochips, LTD (an Arrow Company)

The purpose of this article is to share a strategy on how to verify any simple or complex FSM in an organized, robust, manageable, and efficient way. To verify such FSMs thoroughly we need random scenarios that cover all the possible state transition conditions, corner and boundary conditions, and relevant functional behavior. For that, we require a strong base entity that helps to generate random scenarios to cover all FSM entry-exit conditions and erroneous scenarios easily.
RISC-V Design Verification Strategy

Article - Oct 26, 2020 by Dr. Mike Bartley

As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.
Reducing Area & Power Consumption with Formal-based ‘X’ Verification

Webinar - Oct 15, 2020 by Ping Yeung

In this session we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process.
FPGA Functional Verification Trend Report - 2020

Paper - Oct 13, 2020 by Harry Foster

This report presents the results from the 2020 Wilson Research Group Functional Verification Study focused on the Field-Programmable Gate Array (FPGA) segment. The findings from this study provide invaluable insight into the state of today’s FPGA market in terms of both design and verification trends.
FPGA Functional Verification Trend Report - 2020

Resource (Paper (.PDF)) - Oct 13, 2020 by Harry Foster

This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2020 Wilson Research Group study.