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Questa PropCheck GUI - Source Window

Demo - Oct 10, 2019 by Mark Eslinger

In this session, you will learn how to use the source window.
Questa PropCheck GUI - Waveform View

Demo - Oct 10, 2019 by Mark Eslinger

In this session, you will learn more about the waveform view.
Questa PropCheck GUI - Run Formal

Demo - Oct 10, 2019 by Mark Eslinger

In this session, you will learn how to run Formal from the PropCheck GUI.
Why RDC Verification is an Emerging Requirement

Webinar - Oct 01, 2019 by Kurt Takara

In this session, you will learn what Reset-Domain Crossing (RDC) covers that Clock-Domain Crossing (CDC) does not and the appropriate time in the development cycle to deploy RDC.
Why RDC Verification is an Emerging Requirement

Resource (Slides (.PDF)) - Oct 01, 2019 by Kurt Takara

In this session, you will learn what RDC covers that CDC does not and the appropriate time in the development cycle to deploy RDC.
Questa SLEC Fact Sheet

Resource (Fact Sheet) - Sep 30, 2019 by Nicolae Tusinschi

The Questa SLEC app uses formal analysis to exhaustively compare two blocks of RTL code, identifying any differences in the output behavior of the two designs for all inputs, and for all time.
Stimulus and Analysis Data Flow

Session - Sep 09, 2019 by Bob Oden

In this session, you will be given an overview of the stimulus and analysis flow within the UVM Framework.
Stimulus and Analysis Data Flow

Resource (Slides (.PDF)) - Sep 09, 2019 by Bob Oden
Code Generation Guidelines

Session - Sep 09, 2019 by Bob Oden

In this session, you will be given an overview of the flow used to generate a working simulation using the UVMF code generator.
Code Generation Guidelines

Resource (Slides (.PDF)) - Sep 09, 2019 by Jonathan Craft
Machine-Learning-Assisted Agile VLSI Design for Machine Learning

Resource (Recording) - Aug 31, 2019 by Brucek Khailany

We will highlight two design automation research directions being pursued in the ASIC and VLSI Research group at NVIDIA: (1) An automated C++-to-layout VLSI flow that leverages HLS tools and open-source HLS-compatible C++ libraries for design productivity; and (2) Machine-learning assisted VLSI design techniques. We will also describe our experience using these tools as part of an agile hardware design flow to build for a deep neural network (DNN) inference accelerator testchip.
Assuring the Integrity of RISC-V Cores and SoCs

Resource (Paper (.PDF)) - Aug 21, 2019 by Nicolae Tusinschi

The open RISC-V processor architecture is shaking up the intellectual property (IP) and system-on-chip (SoC) worlds. There is great interest and much industry activity underway. However, successful RISC-V core providers will have to verify all aspects of integrity for their designs: functional correctness, safety, security, and trust. SoC developers evaluating potential RISC-V need to check that their standards for design integrity are fully satisfied.
A New Approach to Low Power Verification - Power Aware Apps

Resource (Paper (.PDF)) - Aug 21, 2019 by Madhur Bhargava

This paper demonstrates how Power Aware Apps can help in reporting, debugging and self-checking low power designs. We will also highlight how these apps will help offer an efficient way to significantly save verification effort and time.
A New Approach to Low Power Verification: Power Aware Apps

Paper - Aug 21, 2019 by Madhur Bhargava

The effective verification of low-power designs has been a challenge for many years now. The IEEE Std 1801-2015 Unified Power Format (UPF) standard for modeling low-power objects and concepts is continuously evolving to address the low-power challenges of today’s complex designs.
Coverage Driven Verification of NVMe Using Questa VIP

Resource (Paper (.PDF)) - Aug 21, 2019 by
Using HLS to Accelerate Computer Vision for Autonomous Drive

Resource (Slides (.PDF)) - Aug 20, 2019 by
Source Code Download: Fun with UVM Sequences - Coding and Debugging

Resource - Aug 20, 2019 by
Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models

Resource (Paper (.PDF)) - Aug 02, 2019 by Thomas Ellis

In this paper we will outline a set of guidelines for writing an unambiguous coverage model.
Technical Paper: Moving Beyond Assertions - An Innovative Approach to Low-Power Checking Using UPF Tcl Apps

Resource - Aug 02, 2019 by
Results Checking Strategies with Portable Stimulus

Resource (Paper (.PDF)) - Aug 02, 2019 by Tom Fitzpatrick

The key to results checking in Portable Stimulus is to understand that different levels of verification and validation environments have different needs when it comes to results checking. In a block-level environment, we might want detailed scoreboarding in addition to an overall per-operation pass/fail. In an SoC environment, we may only need an overall per-operation pass/fail.
Transaction Recording: Anywhere Anytime

Resource (Paper (.PDF)) - Aug 02, 2019 by Rich Edelman

This paper will demonstrate a complete transaction recording system for both a stand-alone implementation and a UVM based implementation
Transaction Recording: Anywhere Anytime

Paper - Aug 02, 2019 by Rich Edelman

Transaction debug can provide visibility where there previously was none. Even in the creation of the examples for this paper, transactions provided several “ah-ha” moments which explained the bug in the example code. It makes debug much faster, requiring only a small amount of work to implement. This paper will demonstrate a complete transaction recording system for both a stand-alone implementation and a UVM based implementation.
Portable Stimulus: Is It Revolution or Evolution?

Conference - Jul 15, 2019 by Tom Fitzpatrick

Many claim the new Portable Test and Stimulus Standard. (PSS) from Accellera will ignite the next revolution in SoC and Electronic System functional verification. Revolutionary innovation seeks to adapt the world to new and better ideas; yet it can be disruptive, expensive and produce unpredicted outcomes.
Portable Stimulus: Is It Revolution or Evolution?

Resource (Slides (.PDF)) - Jul 15, 2019 by Tom Fitzpatrick

In this session, you will learn how Reuse can be the Evolution that enables the PSS Revolution.
An Emulation Strategy for AI and ML Designs

Conference - Jul 15, 2019 by Vijay Chobisa

The ASICs for machine learning applications whether targeted for training or inference will have their own unique characteristics but will nevertheless present quite common and extreme verification challenges that we will present in this session.