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2336 Results
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Understanding the Factory and Configuration
Session - May 25, 2021 by Tom Fitzpatrick
This session shows how tests can use the factory to control the type of components that get instantiated in a UVM environment and how to write environments and components to support customization. It covers the configuration database that allows tests to override configuration information used by environments and components.
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Modeling Transactions
Session - May 25, 2021 by Tom Fitzpatrick
This session outlines the methods needed in the design of a sequence item (a.k.a. “transaction") for use in UVM. It also discusses transaction extension a encapsulation to create more complex transactions.
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Modeling Transactions
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session discusses transaction extension a encapsulation to create more complex transactions.
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How TLM Works
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session covers the design and creation of scoreboard components.
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How TLM Works
Session - May 25, 2021 by Tom Fitzpatrick
This session discusses the use of transaction-level modeling interfaces in UVM to facilitate the creation of modular, hierarchical components. It also covers the design and creation of scoreboard components.
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The Proper Care and Feeding of Sequences
Session - May 25, 2021 by Tom Fitzpatrick
This session covers the creation and execution of sequences, including the interaction of the sequence and driver. It includes the execution of sequential, parallel and hierarchical subsequences.
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The Proper Care and Feeding of Sequences
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session covers the the execution of sequential, parallel and hierarchical subsequences.
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Layered Sequences
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session discusses how to model layered protocols and encapsulate the layering components in a UVC.
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Layered Sequences
Session - May 25, 2021 by Tom Fitzpatrick
This session shows how to create a virtual sequence, which controls the execution of other sequences. It also discusses how to model layered protocols and encapsulate the layering components in a UVC.
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Setting Up the Register Layer
Session - May 25, 2021 by Tom Fitzpatrick
This session introduces the UVM Register Layer, showing you how to create register models that reflect the operation of the hardware registers in your DUT. It shows how to set up the address map of registers and how to convert a register-level transaction into a bus-level transaction. It also shows how the Register Assistant tool can be used to create correct-by-construction register models from a specification.
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Writing and Managing Tests
Session - May 25, 2021 by Tom Fitzpatrick
This session shows how to create a set of tests derived from a base test that defines the default setup of your environment, including how to invoke specific tests from the command line. It also covers how to use phase objections to manage the execution of the test.
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Setting Up the Register Layer
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
In this session, you will learn how to set up the address map of registers and how to convert a register-level transaction into a bus-level transaction.
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Writing and Managing Tests
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session covers how to use phase objections to manage the execution of the test.
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Using the Register Layer
Session - May 25, 2021 by Tom Fitzpatrick
This session discusses the various methods that a test can use to access the register model, including both “front-door” and “back-door” accesses. Using the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.
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Using the Register Layer
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session discusses the Register Layer will also show how to create register-bases stimulus sequences to simplify the API.
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Register-Based Testing
Session - May 25, 2021 by Tom Fitzpatrick
This session shows how to round out your register-based test environment with register-level scoreboards and functional coverage. It also shows how to create memory-based sequences.
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Register-Based Testing
Resource (Slides (.PDF)) - May 25, 2021 by Tom Fitzpatrick
This session shows how to create memory-based sequences.
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Advanced UVM
Track - May 25, 2021 by Tom Fitzpatrick
Advanced UVM builds upon the concepts covered in Basic UVM to take your UVM understanding to the next level.
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The Three Witches: Preventing Glitch Nightmares on CDC Paths
Paper - May 18, 2021 by Ping Yeung
As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. To identify potential glitches at the gate level, Questa Signoff CDC uses structural CDC analysis, expression analysis, and an automated formal-based glitch detection methodology to identify real glitches in a design.
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The Three Witches: Preventing Glitch Nightmares on CDC Paths
Resource (Paper (.PDF)) - May 18, 2021 by Ping Yeung
In this paper, we first explain the glitch problems in various types of CDC paths. Then we summarize an automated formal-based glitch detection methodology.
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Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Resource (Paper (.PDF)) - May 12, 2021 by Michael Fingeroff - Siemens EDA
Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet next-generation machine learning hardware demands at the edge.
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Formal 101: Setting Up and Optimizing Constraints
Session - May 10, 2021 by Mark Eslinger
In this session, we will show you how to write optimal constraints for formal analysis; and how to deliberately under- and over-constrain the analysis to learn more about the effectiveness of the constraints themselves, your test plan and formal coverage plan, and the DUT behavior.
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Setting Up & Optimizing Constraints
Resource (Slides (.PDF)) - May 10, 2021 by
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Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Webinar - May 04, 2021 by Jake Wiltgen
In this session, you will learn details how to effectively set up and execute an ISO 26262 fault campaign for mixed signal designs and establishing an efficient fault injection workflow for analog and digital portions of the design.
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Low Power Considerations for Verification
Webinar - Apr 29, 2021 by Rick Koster
Achieving coverage closure increases with the number of power domains in a design. The UPF add_power_state and add_state_transition commands can help bound the verification state space. In this session we will discuss how to use these commands to manage verification.