FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Register Now!

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Register Now!

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Verification Horizons Blog

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Fremont, CA

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Register Now!

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Register Now!
SIEMENS Verification Academy

Connecting the DUT and Testbench

You will learn about the connection between the testbench and the DUT (Device Under Test) in this informative lesson.

This content is reserved for members. Register new account or login to view.

Full-access members only

Register your account to view Connecting the DUT and Testbench

Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.

Register account