Zhihong Zeng
Zhihong Zeng is a Verification IP Architect at Siemens EDA focusing on PCI, CXL, NVMe and other protocols.
He specializes in simulation based functional verification. He has developed and architected verification IPs for more than 20 years since joined in Avery design systems. Zhihong graduated with a Ph.D. in EDA from the University of Massachusetts Amherst.
Content by Zhihong Zeng
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Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs
Verification IP Mar 26, 2025 Jalaj Gupta Webinar
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