Gabriel Chidolue
Gabriel Chidolue is a Product Engineer in the IC Verification Solutions group within Siemens EDA, a part of Siemens DI SW. He has over 20 years’ experience in Digital design and verification. His current focus area is on functional verification of UPF based Power Managed designs. His main responsibilities include creation and deployment of verification methodologies and solutions in close collaboration with R & D, Siemens EDA Customers, Partners and active participation and contribution within IEEE P1801 WG.
Mr. Chidolue holds a B.Eng in Electrical Engineering from University of Nigeria, Nigeria and an M Sc in Concurrent Engineering for Electronic Product Design from Bournemouth University, United Kingdom.
Content by Gabriel Chidolue
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Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar Paper
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