New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Download 2023.4_2

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Verification Horizons Blog

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

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On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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SIEMENS Verification Academy

Gabriel Chidolue

Gabriel Chidolue is a Product Engineer in the IC Verification Solutions group within Siemens EDA, a part of Siemens DI SW. He has over 20 years’ experience in Digital design and verification. His current focus area is on functional verification of UPF based Power Managed designs. His main responsibilities include creation and deployment of verification methodologies and solutions in close collaboration with R & D, Siemens EDA Customers, Partners and active participation and contribution within IEEE P1801 WG.

Mr. Chidolue holds a B.Eng in Electrical Engineering from University of Nigeria, Nigeria and an M Sc in Concurrent Engineering for Electronic Product Design from Bournemouth University, United Kingdom.

Content by Gabriel Chidolue

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