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June 2015

Resolving the Limitations of a Traditional VIP for PHY Verification
Simulation Jun 06, 2015 Verification Horizons Article
Welcome to the DVCon 2015 issue of Verification Horizons
Simulation Jun 06, 2015 Verification Horizons Article
Automating the Capture of Assertion Verification Results for DO-254
Functional Safety Jun 06, 2015 Vipul Patel - Einfochips Article
DO-254 Testing of High-Speed FPGA Interfaces
Functional Safety Jun 06, 2015 Nir Weintroub, Sani Jabsheh - Verisense Article
Formal and Assertion-Based Verification of MBIST MCPs
Assertions Jun 06, 2015 Ajay Daga - Fishtail Design Automation Article
Reuse MATLAB® Functions and Simulink® Models in UVM Environments with Automatic SystemVerilog DPI Component Generation
SystemVerilog Jun 06, 2015 Tao Jia, Jack Erickson - Mathworks Article
Starting Formal Right from Formal Test Planning
Formal Verification Jun 06, 2015 Jin Zhang Article
Unit Testing Your Way to a Reliable Testbench
Simulation Jun 06, 2015 Neil Johnson Article
Hardware Emulation: Three Decades of Evolution – Part II
Acceleration Jun 06, 2015 Dr. Lauro Rizzatti - Rizzatti Llc Article

March 2015

Power Aware RTL Verification of USB 3.0 IPs
Low Power Mar 11, 2015 Gayathri Sn, Badrinath Ramachandra - L&T Technology Services Limited Article
Increase Verification Productivity with Questa® UVM Debug
Standards Mar 11, 2015 Verification Horizons Article
Fast Track to Productivity Using Questa® Verification IP
Simulation Mar 11, 2015 Verification Horizons Article
MIPI LLI Verification using Questa Verification IP
Verification IP Mar 11, 2015 Verification Horizons Article
Merging SystemVerilog Covergroups by Example
Standards Mar 11, 2015 Verification Horizons Article
Small, Maintainable Tests
Simulation Mar 11, 2015 Verification Horizons Article

December 2014

Dealing With UVM and OVM Sequences
Standards Dec 29, 2014 Verification Horizons Article
Don't Forget the Little Things That Can Make Verification Easier
Simulation Dec 29, 2014 Verification Horizons Article
Cache Coherent Interface Verification IP
Simulation Dec 17, 2014 Verification Horizons Article

November 2014

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide
Simulation Nov 20, 2014 Verification Horizons Article
Hey You, Design Engineer!
Analog Mixed-Signal Nov 20, 2014 Verification Horizons Article
Flexible UVM Components: Configuring Bus Functional Models
Standards Nov 19, 2014 Verification Horizons Article
NoC Generic Scoreboard VIP
Simulation Nov 19, 2014 Verification Horizons Article
Using Mentor Questa® for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments
Simulation Nov 19, 2014 Verification Horizons Article
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
Simulation Nov 11, 2014 Verification Horizons Article

July 2014

ST-Ericsson Speeds Time to Functional Verification Closure with Questa Verification Platform
Simulation Jul 10, 2014 Verification Horizons Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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