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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

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June 2016 - Volume 12 Issue 2 (8)

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Messaging (8)

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July 2020 - Volume 16 Issue 2 (7)

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March 2015 - Volume 11 Issue 1 (7)

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November 2014 - Volume 10 Issue 3 (7)

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December 2017 - Volume 13 Issue 3 (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

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March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

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VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

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December 2019 - Volume 15 Issue 3 (5)

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February 2019 - Volume 15 Issue 1 (5)

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March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

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VA Live 2019 - Westford (5)

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HBM (4)

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IEEE (4)

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November 2018 - Volume 14 Issue 3 (4)

Objectives (4)

PCIe Gen 6 (4)

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UART (4)

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VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

VA Live 2025 - Scottsdale (4)

VA Live 2026 - Austin (4)

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VPM (4)

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$display (3)

1.2 (3)

AHB (3)

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GPU (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

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Function (2)

GLS (2)

GOMACTech (2)

Glitch Detection (2)

Governance (2)

Graph-Based Stimulus (2)

Hallucination (2)

Hardening (2)

Hardware / Software (2)

Hardware Behavior (2)

Hardware Debugging (2)

Heterogeneous (2)

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June 2012

Relieving the Parameterized Coverage Headache
Coverage Jun 15, 2012 Bryan Ramirez Article
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
FPGA Verification Jun 15, 2012 Stephan Van Beek, Sudhir Sharma, Sudeepa Prakash - Mathworks Article
Better Living Through Better Class-Based SystemVerilog Debug
SystemVerilog Jun 15, 2012 Rich Edelman Article
Verification Horizons - Volume 8, Issue 2
Standards Jun 15, 2012 Tom Fitzpatrick pdf
Introduction to Metrics
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster Session
The Driving Forces for Change
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What Can Metrics Tell Us?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What's Needed to Address the Problem?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What's Needed to Adopt Metrics?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Evolving Trends in Functional Verification
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster pdf
What to Expect After Adopting the Metrics
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
Metrics in SoC Verification
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Track

May 2012

Introduction to UVM Connect
UVMC May 31, 2012 Adam Erickson Session
Introduction to UVM Connect
UVMC May 31, 2012 Adam Erickson pdf
Connections
UVMC May 31, 2012 Adam Erickson pdf
Connections
UVMC May 31, 2012 Adam Erickson Session
Converters
UVMC May 31, 2012 Adam Erickson Session
Converters
UVMC May 31, 2012 Adam Erickson pdf
UVM Command API
UVMC May 31, 2012 Adam Erickson Session
UVM Command API
UVMC May 31, 2012 Adam Erickson pdf
UVM Connect User Guide
UVMC May 31, 2012 Adam Erickson pdf
UVM 1.1b Class Reference
UVM - Universal Verification Methodology May 21, 2012 html

February 2012

UVM Connect 2.1.4 Kit
UVMC Feb 20, 2012 John Stickley tar
Verification Horizons - Volume 8, Issue 1
Standards Feb 01, 2012 Tom Fitzpatrick pdf

December 2011

UVM 1.1a Class Reference
UVM - Universal Verification Methodology Dec 01, 2011 html

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

VA Live - Hudson, MA

Tuesday, June 9, 2026 | 9:00 AM - 5:00 PM EDT

This seminar empowers design engineers and verification teams with knowledge and tools for advanced AI automation and intelligent verification.

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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