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September 2021 - Volume 17 Issue 2 (12)

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November 2018 - Volume 14 Issue 3 (4)

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June 2017 - Volume 13 Issue 2 (2)

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March 2017 - Volume 13 Issue 1 (2)

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March 2016 - Volume 12 Issue 1 (1)

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September 2012

Protocol Layering
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Introduction to UVM Registers
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
C-Based Stimulus for UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
UVM Debug
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Scoreboards and Results Predictors in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
OVM to UVM Migration
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Customization in UVM
UVM - Universal Verification Methodology Sep 17, 2012 Tom Fitzpatrick Webinar
Improving FPGA Debugging with Assertions
FPGA Verification Sep 10, 2012 Harry Foster Article
UVM Connect 2.2 Kit
UVMC Sep 07, 2012 John Stickley tar

August 2012

FPGA Verification Capabilities
FPGA Verification Aug 30, 2012 Ray Salemi Track
Introduction from Harry Foster
FPGA Verification Aug 30, 2012 Harry Foster Session
Overview and Welcome
FPGA Verification Aug 30, 2012 Ray Salemi Session
Code Coverage
FPGA Verification Aug 30, 2012 Ray Salemi Session
Test Planning
FPGA Verification Aug 30, 2012 Ray Salemi Session
Applied Assertions
FPGA Verification Aug 30, 2012 Ray Salemi Session
Transactions
FPGA Verification Aug 30, 2012 Ray Salemi Session
Self-Checking Testbenches
FPGA Verification Aug 30, 2012 Ray Salemi Session
Automatic Stimulus
FPGA Verification Aug 30, 2012 Ray Salemi Session
Functional Coverage
FPGA Verification Aug 30, 2012 Ray Salemi Session

June 2012

Using the UVM Register Layer
UVM - Universal Verification Methodology Jun 22, 2012 John Aynsley pdf
On the Fly Reset
UVM - Universal Verification Methodology Jun 15, 2012 Mark Peryer Article
Introduction to Metrics
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster Session
The Driving Forces for Change
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What Can Metrics Tell Us?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What's Needed to Address the Problem?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session

PCIe Gen7 Webinar

Wednesday, Mar 26th-10:00 AM PDT

Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs

Simulation Webinar

Wednesday, Apr 16th-8:00 AM PDT

Faster Debug Using QuestaSim Interactive Coverage Analysis

FPGA Design Webinar

Wednesday, Apr 23rd-8:00 AM PDT

Securing your FPGA Design from RTL through to the Bitstream

Browse all content in Siemens Verification Academy with the tag february 2013 - volume 9 issue 1

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September 2012

Protocol Layering

Introduction to UVM Registers

C-Based Stimulus for UVM

UVM Debug

Scoreboards and Results Predictors in UVM

OVM to UVM Migration

Customization in UVM

Improving FPGA Debugging with Assertions

UVM Connect 2.2 Kit

August 2012

FPGA Verification Capabilities

Introduction from Harry Foster

Overview and Welcome

Code Coverage

Test Planning

Applied Assertions

Transactions

Self-Checking Testbenches

Automatic Stimulus

Functional Coverage

June 2012

Using the UVM Register Layer

On the Fly Reset

Introduction to Metrics

The Driving Forces for Change

What Can Metrics Tell Us?

What's Needed to Address the Problem?