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May 2012

Converters
UVMC May 31, 2012 Adam Erickson Session
Converters
UVMC May 31, 2012 Adam Erickson pdf
UVM Command API
UVMC May 31, 2012 Adam Erickson Session
UVM Command API
UVMC May 31, 2012 Adam Erickson pdf
UVM Connect User Guide
UVMC May 31, 2012 Adam Erickson pdf
UVM 1.1b Class Reference
UVM - Universal Verification Methodology May 21, 2012 html

February 2012

UVM Connect 2.1.4 Kit
UVMC Feb 20, 2012 John Stickley tar

December 2011

UVM 1.1a Class Reference
UVM - Universal Verification Methodology Dec 01, 2011 html

October 2011

Testbench Co-Emulation: SystemC & TLM-2.0
Acceleration Oct 27, 2011 John Stickley Track
Introduction to SystemC & TLM 2.0
Acceleration Oct 27, 2011 John Stickley Session
SystemC & TLM-2.0 Testbench Modeling
Acceleration Oct 27, 2011 John Stickley Session
The SCE-MI 2.0 Standard
Acceleration Oct 27, 2011 John Stickley Session
The OSCI TLM-2.0 Standard
Acceleration Oct 27, 2011 John Stickley Session
Modeling SystemC TLM-2.0 Drivers
Acceleration Oct 27, 2011 John Stickley Session
SystemC & TLM-2.0 Monitors and Talkers
Acceleration Oct 27, 2011 John Stickley Session

August 2011

Advanced Debug with Questa
Debug Aug 01, 2011 pdf

April 2011

Transforming Verification and Verification Management
Verification Management Apr 08, 2011 Tom Fitzpatrick Webinar
Power Aware Verification & UPF Tricks
Low Power Apr 08, 2011 Tom Fitzpatrick Webinar

March 2011

Are OVM & UVM Macros Evil? A Cost-Benefit Analysis
UVM - Universal Verification Methodology Mar 08, 2011 Adam Erickson pdf

February 2011

CDC Verification
Clock-Domain Crossing Feb 25, 2011 Harry Foster Track
Overview and Welcome
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Introduction to CDC
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Understanding Metastability
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Metastability Verification Flow
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session
Modeling Metastability
Clock-Domain Crossing Feb 25, 2011 Harry Foster Session

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag sata

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