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June 2020

Introduction to Visualizer for the VHDL Users
Debug Jun 30, 2020 Rich Edelman Webinar
Introduction to Visualizer for the Verilog Users
Debug Jun 16, 2020 Rich Edelman Webinar
Better UVM Debug
UVM - Universal Verification Methodology Jun 02, 2020 tar
Better UVM Debug with Visualizer
Debug Jun 02, 2020 Rich Edelman Webinar

April 2020

UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know
SystemVerilog Apr 10, 2020 Chris Spear Webinar
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft pdf
Code Generation Merging
UVM Framework Apr 01, 2020 Jonathan Craft Session

March 2020

Verify Thy Verifyer
UVM - Universal Verification Methodology Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - Verifworks Article

September 2019

Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden Session
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Bob Oden Session
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Source Code Download: Fun with UVM Sequences - Coding and Debugging
Standards Aug 20, 2019 tar
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman pdf
Transaction Recording: Anywhere Anytime
UVM - Universal Verification Methodology Aug 02, 2019 Rich Edelman Paper

July 2019

DAC 2019 Academy PDF Presentation: Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer
Standards Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: What's Missing and What Should Be Next for SystemVerilog
Standards Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: Debugging Your Design in a Heterogeneous Environment
Standards Jul 10, 2019 pdf

June 2019

Transaction Recording & Debug with Questa & Visualizer
Debug Jun 20, 2019 Rich Edelman Webinar
Fun with UVM Sequences - Coding and Debugging
UVM - Universal Verification Methodology Jun 03, 2019 Rich Edelman Article

April 2019

Block level testbench (.tgz)
UVM - Universal Verification Methodology Apr 19, 2019 tar
UVM Monitor
UVM - Universal Verification Methodology Apr 02, 2019 tar
Block level testbench
UVM - Universal Verification Methodology Apr 02, 2019 tar

February 2019

UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman Paper
UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergistic Flows for Next-Gen Verification

UALink VIP Webinar

Wednesday, Oct 15th-10:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

DVCon Europe 2025

October 14th - 15th | Munich, Germany

osmosis Europe 2025

October 16th | Munich, Germany

RISC-V Summit 2025

October 22nd - 23rd | Santa Clara, CA

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

Portable Stimulus Webinar

Wednesday, Oct 29th-10:00 AM PDT

Portable Stimulus: What can it do for me? | Presented by Doulos

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

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