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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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UVM 1.1d (3)

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Thread Control (2)

Throughout (2)

Timing Integrity (2)

Transaction Layer (2)

Transmitter IP (2)

Transport Layer (2)

Trend Analysis (2)

UCIS (2)

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June 2017

MIPI® CSI-2 TX Verification
Verification IP Jun 13, 2017 Ivan Ristic Seminar
Leveraging the latest DDR & Flash Memory Models
Verification IP Jun 13, 2017 Jason Polychronopoulos Seminar
USB 3.1 Verification Challenges
Verification IP Jun 13, 2017 Dinesh Tyagi Seminar
Conquering the New IP Economy
Planning, Measurement and Analysis Jun 13, 2017 Harry Foster Seminar

May 2017

SoC Verification with the Questa Flow
FPGA Verification May 17, 2017 Gordon Allan Webinar

March 2017

Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar Paper
Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
Low Power Mar 20, 2017 Progyna Khondkar pdf
Testbench Automation - Environment
UVM Framework Mar 17, 2017 Bob Oden Conference
Testbench Automation - Introduction
UVM Framework Mar 17, 2017 Bob Oden Conference
Testbench Automation - Testbench
UVM Framework Mar 17, 2017 Bob Oden Conference
Testbench Automation - Interfaces
UVM Framework Mar 17, 2017 Bob Oden Conference
Use Formal to Check Logic Faults
Formal Verification Mar 17, 2017 Mark Eslinger Webinar
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Thomas Ellis Paper
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Thomas Ellis pdf
Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee
Verification Management Mar 13, 2017 Thomas Ellis pdf
Will Safety Critical Design Practices Improve First Silicon Success?
Functional Safety Mar 01, 2017 Harry Foster Article
A Practical Methodology for Meeting ISO 26262 Random Faults Safety Goals in Automotive Semiconductor Products
Functional Safety Mar 01, 2017 Jamil R. Mazzawi, Amir N. Rahat - Optima Design Automation Ltd. Article
Automating Tests with Portable Stimulus from IP to SoC Level
Portable Stimulus Mar 01, 2017 Matthew Ballance Article
UVM Tips and Tricks
UVM - Universal Verification Methodology Mar 01, 2017 Sandeep Nasa, Shankar Arora - Logic Fruit Technologies Pvt. Ltd. Article
Artifacts of Custom Checkers in Questa Power Aware Dynamic Simulation
Low Power Mar 01, 2017 Progyna Khondkar Article
Complementing Functional Verification Through the Use of Available Timing Information
Clock-Domain Crossing Mar 01, 2017 Rick Eram - Excellicon Article

February 2017

How Formal Reduces Fault Analysis for ISO 26262
Functional Safety Feb 15, 2017 Doug Smith Paper
How Formal Reduces Fault Analysis for ISO 26262
Functional Safety Feb 15, 2017 Doug Smith pdf

January 2017

Questa VRM and Jenkins
Planning, Measurement and Analysis Jan 10, 2017 Darron May Track
Jenkins Installation and Setup
Planning, Measurement and Analysis Jan 10, 2017 Darron May Session

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

VHDL Webinar

Wednesday, Nov 12th-8:00 AM PST

Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

User2User

Nov. 19th | 0800 - 1630 US/Eastern

Mid-Atlantic 2025 | Johns Hopkins University | Laurel, Maryland

Debug Webinar

Wednesday, Dec 03rd-8:00 AM PST

VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

Verification Academy Live

Scottsdale, AZ | Dec. 3rd - 9:30 - 5:00 US/MST | Top Golf

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