Instantiating the DUT
In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench. You will also learn how to connect bus functional models to primary DUT ports as well as internal DUT interfaces.
In this session, you will learn how to compile and instantiate a Verilog and VHDL DUT within a UVMF testbench. You will also learn how to connect bus functional models to primary DUT ports as well as internal DUT interfaces.