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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2015 - Volume 11 Issue 2 (11)

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June 2012 - Volume 8 Issue 2 (9)

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June 2018 - Volume 14 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

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osmosis 2023 A&D (8)

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Bind (7)

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Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

LLMs (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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Monitor (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

Order Property Pattern (7)

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Testbench Customization in UVM (7)

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VA Live 2023 - Huntsville (7)

Verification Complete (7)

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XML (7)

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Appendix (6)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Design Constraints (6)

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IP Integration (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MBIST (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

Power Efficiency (6)

Pre-Silicon (6)

Random Faults (6)

Respins (6)

Slave (6)

Static & Formal Adoption (6)

Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

Verbosity (6)

Verification Effectiveness (6)

Visualization (6)

Windows (6)

X-Effects (6)

YAML (6)

osmosis 2024 A&D (6)

ATPG (5)

Advance Your Verification Methodology (5)

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BIST (5)

Base Class (5)

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Callbacks (5)

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Constraint Solver (5)

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Coverage Holes (5)

DAC 2024 (5)

DSP (5)

Data Encryption (5)

December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Scaling (5)

Digital Twin (5)

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Error (5)

FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

HBM4 (5)

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High-Speed (5)

IDE (5)

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Low Power Verification Forum (5)

MARLUG 2024 (5)

MARLUG 2025 (5)

March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

NVM Express (5)

Namespaces (5)

Post-silicon Debug (5)

Precedence (5)

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Prototyping (5)

Quirky (5)

Repository (5)

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Simulink (5)

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VA Live 2019 - Westford (5)

VA Live 2023 - Westford (5)

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VA Live 2024 - Westford (5)

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C++ (4)

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DVFS (4)

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IEEE (4)

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Metastability Injection (4)

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Non-Pipelined (4)

Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

Partitioning (4)

Phase Objections (4)

Phases (4)

Plusargs (4)

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QoR (4)

Questa Design Solutions (4)

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SVTB (4)

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Syntax (4)

Tcl/Tk (4)

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Test Ranking (4)

Time Cone (4)

UART (4)

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UPF 4.0 (4)

USB (4)

Unified Coverage Database (4)

Unreachability (4)

Use Models (4)

Utilization (4)

VA Live 2023 - Austin (4)

VA Live 2024 - Austin (4)

VA Live 2024 - Fremont (4)

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$display (3)

1.2 (3)

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Airborne Electronic Hardware (3)

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CSI-2 (3)

Case Statements (3)

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Clocking (3)

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Cryptography (3)

Data Processing (3)

Delay Loops (3)

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Dual Top (3)

ESL (3)

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Exhaustive (3)

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Fibre Channel (3)

Formal Verification Apps (3)

Golden Model (3)

HLV (3)

Handles (3)

Hardware Architecture (3)

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Hardware Verification (3)

Horizontal Reuse (3)

IC Design (3)

Integrity Challenges (3)

Intelligent Integration (3)

JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

NRRs (3)

NoC (3)

OSVVM (3)

Objectives (3)

Observer (3)

Open Architecture (3)

PCI-SIG (3)

PHY (3)

Parallel Compile (3)

Parallel Computing (3)

Phase-Level (3)

Polymorphic Behavior (3)

Power Architecture (3)

Power Gating (3)

Profiling (3)

Protocol Layers (3)

QEMU (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

RTL Sign-Off (3)

Radiation Mitigation (3)

Re-Spins (3)

Re-targeting (3)

Real Number Modeling (3)

Reconfiguration (3)

Resource Utilization (3)

Routines (3)

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Security Coverage (3)

Security Vulnerabilities (3)

Semantics (3)

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Semiconductor (3)

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Serial Interface (3)

Singleton (3)

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Source Code Management (3)

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State Transition (3)

Static Lists (3)

Static Properties (3)

Stream (3)

TBX (3)

TDISP (3)

Test Coverage (3)

Test Realization (3)

Transfer Protocols (3)

Transitive (3)

Trust Verification (3)

Type Casting (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

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UVMC 2.3.4 (3)

Unidirectional (3)

Unreachable Code (3)

VA Live 2026 - El Segundo (3)

VHDL-2019 (3)

VIP - 3.1 (3)

VbyOne (3)

Verification Cycles (3)

Verification Framework (3)

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X-State (3)

2D/3D (2)

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ALU (2)

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CSI (2)

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GLS (2)

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Hybrid Virtual Platform (2)

IEEE 754 (2)

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Implies (2)

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Instantiate (2)

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Intersect (2)

JTAG (2)

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LVS (2)

Last Mile Problem (2)

Latch-Based Designs (2)

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Liberty Syntax (2)

LockGrab (2)

Lockstep (2)

Logic Cone (2)

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MBSE (2)

MUX (2)

Machine Readable Specification (2)

Makefile (2)

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Memory BIST (2)

Memory Blocks (2)

Memory-based Sequences (2)

Metric Analyzers (2)

Multi-Clock Designs (2)

Multi-Language Environment (2)

Network ID Mapping (2)

Noise Reduction (2)

On-Chip (2)

OnChip (2)

Open Bus Interface (2)

PAM4 (2)

Packet Transfer (2)

Parameter-to-Signal (2)

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May 2018

What is Formal, Anyway
Formal Verification May 14, 2018 pdf
Instant Formal Expert
Formal Verification May 14, 2018 pdf
What is Formal, Anyway?
Formal Verification May 14, 2018 Doug Smith Session

April 2018

Running Simulations
UVM Framework Apr 16, 2018 Jonathan Craft pdf
Running Simulations
UVM Framework Apr 16, 2018 Jonathan Craft Session
UVMF & Emulation
UVM Framework Apr 16, 2018 Mike Horn pdf
Basic Abstraction Techniques
Formal Verification Apr 14, 2018 pdf
Sequence Categories
UVM Framework Apr 12, 2018 Bob Oden pdf
Sequence Categories
UVM Framework Apr 12, 2018 Bob Oden Session
Adding Tests and Sequences
UVM Framework Apr 12, 2018 Bob Oden pdf
Adding Tests and Sequences
UVM Framework Apr 12, 2018 Bob Oden Session
Instantiating the DUT
UVM Framework Apr 12, 2018 Bob Oden Session
Instantiating the DUT
UVM Framework Apr 12, 2018 Bob Oden pdf
Bench Code Generation
UVM Framework Apr 12, 2018 Jonathan Craft Session
Bench Code Generation
UVM Framework Apr 12, 2018 Jonathan Craft pdf
Probe Class
SystemVerilog Apr 01, 2018 Dave Rich link

March 2018

Scoreboards
UVM - Universal Verification Methodology Mar 31, 2018 Verification Methodology Team Chapter
Pipelined Protocols
UVM - Universal Verification Methodology Mar 31, 2018 Verification Methodology Team Chapter
UVM Components
UVM - Universal Verification Methodology Mar 27, 2018 Verification Methodology Team Chapter
How Formal Reduces Fault Analysis for ISO 26262
Functional Safety Mar 27, 2018 Doug Smith Conference
Requirement Tracing in the ISO 26262 World
Functional Safety Mar 27, 2018 Charles Battikha Webinar
ISO 26262: Compliant Verification From Analysis to Fault Campaigns
Functional Safety Mar 27, 2018 Doug Smith Conference
Block Level Testbench
UVM - Universal Verification Methodology Mar 24, 2018 Verification Methodology Team Chapter
Integration Level Testbench
UVM - Universal Verification Methodology Mar 23, 2018 Verification Methodology Team Chapter
Testbench Architecture
UVM - Universal Verification Methodology Mar 21, 2018 Verification Methodology Team Chapter