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November 2018 - Volume 14 Issue 3 (4)

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July 2023 - Volume 19 Issue 2 (3)

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UVM 1.1d (3)

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Transmitter IP (2)

Transport Layer (2)

Trend Analysis (2)

UCIS (2)

Ultra Accelerator Link (2)

Universal Approximation (2)

Unreachability (2)

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January 2019

ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

December 2018

How to Unearth Deep Bugs Using Formal Bug Hunting Techniques
Formal Verification Dec 23, 2018 Mark Eslinger Webinar
Full-Featured SOC Debug Cross-Triggering
Simulation Dec 10, 2018 Verification Methodology Team Article
C Stimulus Package (.tgz)
UVM - Universal Verification Methodology Dec 04, 2018 Verification Methodology Team tar

November 2018

FPGA Verification Challenges and Opportunities
FPGA Verification Nov 28, 2018 Harry Foster Article
Building a Better Virtual Sequence with Portable Stimulus
Portable Stimulus Nov 28, 2018 Matthew Ballance Article
A New Approach to Low Power Verification: Power Aware Apps
Low Power Nov 28, 2018 Madhur Bhargava, Awashesh Kumar - Siemens Eda Article
Simplifying Mixed-Signal Verification
Analog Mixed-Signal Nov 28, 2018 Article

October 2018

Functional Verification Study - 2018
Planning, Measurement and Analysis Oct 15, 2018 Harry Foster Session
Planning for DO-254
Functional Safety Oct 10, 2018 Byron Brinson pdf
Planning for DO-254
Functional Safety Oct 10, 2018 Byron Brinson Session
DO-254 in Simple Terms
Functional Safety Oct 04, 2018 Byron Brinson Session
DO-254 in Simple Terms
Functional Safety Oct 04, 2018 Byron Brinson pdf
Introduction to DO-254
Functional Safety Oct 04, 2018 Byron Brinson Track

September 2018

UVM 1800.2 and the New & Improved Cookbook
UVM - Universal Verification Methodology Sep 27, 2018 pdf
A Fresh Look at Creating a UVM Environment - UVM Framework
UVM Framework Sep 27, 2018 pdf
A Fresh Look at Creating a UVM Environment - All Slides
UVM - Universal Verification Methodology Sep 27, 2018 zip
A Fresh Look at Creating a UVM Environment - Introduction
UVM - Universal Verification Methodology Sep 27, 2018 pdf
Vista Virtual Prototyping
Functional Safety Sep 27, 2018 pdf
Visualizer Debug Introduction
Debug Sep 27, 2018 pdf
UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick pdf
UVM 1800.2 & The New and Improved UVM Cookbook
UVM - Universal Verification Methodology Sep 11, 2018 Tom Fitzpatrick Webinar
UVM
UVM - Universal Verification Methodology Sep 05, 2018 Verification Methodology Team Cookbook

August 2018

UVM-2017 v0.9 Library Code for IEEE 1800.2
UVM - Universal Verification Methodology Aug 29, 2018 tar
UVM 2017-1.0 Reference Implementation
UVM - Universal Verification Methodology Aug 29, 2018 tar

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

HLS Webinar

Wednesday, Nov 05th-8:00 AM PST

Formal Verification of Synthesizable C++/SystemC Designs

VHDL Webinar

Wednesday, Nov 12th-8:00 AM PST

Don't Let VHDL Debugging Slow You Down! Use Questa One Sim

User2User

Nov. 19th | 0800 - 1630 US/Eastern

Mid-Atlantic 2025 | Johns Hopkins University | Laurel, Maryland

Debug Webinar

Wednesday, Dec 03rd-8:00 AM PST

VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim

Verification Academy Live

Scottsdale, AZ | Dec. 3rd - 9:30 - 5:00 US/MST | Top Golf

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