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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

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July 2020 - Volume 16 Issue 2 (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

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VA Live 2023 - Huntsville (7)

Verification Complete (7)

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XML (7)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

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March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

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Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

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Visualization (6)

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YAML (6)

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ATPG (5)

Advance Your Verification Methodology (5)

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DAC 2024 (5)

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December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Scaling (5)

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February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

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March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

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Quirky (5)

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VA Live 2019 - Westford (5)

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IEEE (4)

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Non-Pipelined (4)

Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

Partitioning (4)

Phase Objections (4)

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UART (4)

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UPF 4.0 (4)

USB (4)

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Unreachability (4)

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VA Live 2023 - Austin (4)

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1.2 (3)

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Golden Model (3)

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Handles (3)

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Horizontal Reuse (3)

IC Design (3)

Integrity Challenges (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathematical Analysis (3)

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NRRs (3)

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Observer (3)

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PCI-SIG (3)

PHY (3)

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Phase-Level (3)

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Power Architecture (3)

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Profiling (3)

Protocol Layers (3)

QEMU (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

RTL Sign-Off (3)

Radiation Mitigation (3)

Re-Spins (3)

Re-targeting (3)

Real Number Modeling (3)

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Routines (3)

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Singleton (3)

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Stream (3)

TBX (3)

TDISP (3)

Test Coverage (3)

Test Realization (3)

Transfer Protocols (3)

Transitive (3)

Trust Verification (3)

Type Casting (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

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Unidirectional (3)

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VA Live 2026 - El Segundo (3)

VHDL-2019 (3)

VIP - 3.1 (3)

VbyOne (3)

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IEEE 754 (2)

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JTAG (2)

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Logic Cone (2)

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MBSE (2)

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Makefile (2)

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Memory Blocks (2)

Memory-based Sequences (2)

Metric Analyzers (2)

Multi-Clock Designs (2)

Multi-Language Environment (2)

Network ID Mapping (2)

Noise Reduction (2)

On-Chip (2)

OnChip (2)

Open Bus Interface (2)

PAM4 (2)

Packet Transfer (2)

Parameter-to-Signal (2)

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July 2020

Effective Validation Method of Safety Mechanism Compliant with ISO 26262
Functional Safety Jul 19, 2020 Toshiyuki Hamatani - Verification Technology, Inc. Article
When Are You Done Running CDC?
Clock-Domain Crossing Jul 16, 2020 Chris Giles Webinar
When Are You Done Running CDC?
Clock-Domain Crossing Jul 16, 2020 Chris Giles pdf
Get Your Bits Together: SystemVerilog Structures and Packages
SystemVerilog Jul 14, 2020 Chris Spear Webinar
Simplifying Questa Usage and Deployment with Qrun
FPGA Verification Jul 09, 2020 Tom Kiley Webinar

June 2020

Introduction to Visualizer for VHDL Users
Debug Jun 30, 2020 Rich Edelman Webinar
Introduction to Visualizer for Verilog Users
Debug Jun 16, 2020 Rich Edelman Webinar
ISO 26262 Functional Safety for Autonomous Vehicles
Functional Safety Jun 11, 2020 Jake Wiltgen Webinar
Confronting Inevitability: Finding Clock and Reset Issues Before They Find You
Clock-Domain Crossing Jun 11, 2020 Chris Giles Webinar
Taking SystemVerilog Arrays to the Next Dimension
SystemVerilog Jun 05, 2020 Chris Spear Webinar
Automated Formal-Based Apps: Improving Quality and Time-to-Market with Formal
Formal Verification Jun 04, 2020 Joe Hupcey Webinar
Direct Formal Property Checking: Improving Quality and Time-to-Market with Formal
Formal Verification Jun 04, 2020 Mark Eslinger Webinar
Deadlock Verification for Dummies: The Easy Way Using SVA and Formal
Formal Verification Jun 02, 2020 Mark Eslinger Webinar
Better UVM Debug
UVM - Universal Verification Methodology Jun 02, 2020 tar
Better UVM Debug with Visualizer
Debug Jun 02, 2020 Rich Edelman Webinar

May 2020

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP
Verification IP May 28, 2020 Munish Goyal Webinar
Market-Driven Trends in Hardware Emulation
Acceleration May 21, 2020 Vijay Chobisa Webinar
Context Aware Debug for Complex Heterogeneous Environments
Debug May 21, 2020 Rich Edelman Webinar
Productivity in the Questa Simulation Flow
Simulation May 15, 2020 Gordon Allan Webinar
Optimizing Time to Bug
Planning, Measurement and Analysis May 15, 2020 Tom Fitzpatrick Webinar

April 2020

ISO 26262 Requirements Management
Functional Safety Apr 21, 2020 Jake Wiltgen Session
ISO 26262 in Simple Terms
Functional Safety Apr 21, 2020 Jake Wiltgen Session
ISO 26262 in Simple Terms
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
ISO 26262 Requirements Management
Functional Safety Apr 21, 2020 Jacob Wiltgen pdf
Introduction to ISO 26262
Functional Safety Apr 20, 2020 Jake Wiltgen Track

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July 2020

Effective Validation Method of Safety Mechanism Compliant with ISO 26262

When Are You Done Running CDC?

When Are You Done Running CDC?

Get Your Bits Together: SystemVerilog Structures and Packages

Simplifying Questa Usage and Deployment with Qrun

June 2020

Introduction to Visualizer for VHDL Users

Introduction to Visualizer for Verilog Users

ISO 26262 Functional Safety for Autonomous Vehicles

Confronting Inevitability: Finding Clock and Reset Issues Before They Find You

Taking SystemVerilog Arrays to the Next Dimension

Automated Formal-Based Apps: Improving Quality and Time-to-Market with Formal

Direct Formal Property Checking: Improving Quality and Time-to-Market with Formal

Deadlock Verification for Dummies: The Easy Way Using SVA and Formal

Better UVM Debug

Better UVM Debug with Visualizer

May 2020

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP

Market-Driven Trends in Hardware Emulation

Context Aware Debug for Complex Heterogeneous Environments

Productivity in the Questa Simulation Flow

Optimizing Time to Bug

April 2020

ISO 26262 Requirements Management

ISO 26262 in Simple Terms

ISO 26262 in Simple Terms

ISO 26262 Requirements Management

Introduction to ISO 26262