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Show Less

June 2023

Easy Testbench Evolution: Styling Sequences and Drivers
UVM - Universal Verification Methodology Jun 22, 2023 Rich Edelman pdf

March 2023

Rapid Testbench Development
UVM Framework Mar 07, 2023 Bob Oden pdf

February 2023

Simulating UVMF Code on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman Session
Simulating UVMF Code on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman pdf
Generating UVMF Code on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman Session
Generating UVMF Code on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman pdf
Installing Python on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman Session
Installing Python on Windows
UVM Framework Feb 20, 2023 Graeme Jessiman pdf
UVMF Build/Compile/Run Script Introduction
UVM Framework Feb 20, 2023 Jonathan Craft Session
UVMF Build/Compile/Run Script
UVM Framework Feb 20, 2023 Jonathan Craft pdf
Register Adapters, Predictors, and Tests
UVM Framework Feb 20, 2023 Nick Galvan pdf
Register Adapters, Predictors and Tests
UVM Framework Feb 20, 2023 Nick Galvan Session
Register Model Generation and Replacement
UVM Framework Feb 20, 2023 Nick Galvan Session
Register Model Generation and Replacement
UVM Framework Feb 20, 2023 Nick Galvan pdf
Register Model Generation and Integration
UVM Framework Feb 20, 2023 Nick Galvan Session
Register Model Generation and Integration
UVM Framework Feb 20, 2023 Nick Galvan pdf

January 2023

The UVM Factory Revealed - Part 1
UVM - Universal Verification Methodology Jan 20, 2023 Chris Spear link

October 2022

UVM Testbench Debug – A Day At The Beach – Right?
Debug Oct 04, 2022 Rich Edelman link

July 2022

Easy Testbench Speedups
SystemVerilog Jul 05, 2022 Eileen Hickey - Doulos Inc. Article

June 2022

Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman Paper
Register Modeling: Exploring Fields, Registers and Address Maps
UVM - Universal Verification Methodology Jun 23, 2022 Rich Edelman pdf

May 2022

Create a UVM Testbench in a Day Using a Rapid, Repeatable Approach
UVM Framework May 10, 2022 Bob Oden Webinar

March 2022

What Does the Sequence Say? Powering Productivity with Polymorphism
UVM - Universal Verification Methodology Mar 23, 2022 Rich Edelman pdf
What Does the Sequence Say? Powering Productivity with Polymorphism
UVM - Universal Verification Methodology Mar 23, 2022 Rich Edelman Paper

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

Agentic AI Webinar

Wednesday, Apr 22nd-8:00 AM PDT

From Apps to Orchestration: Agentic AI for Autonomous RTL Signoff with Questa One Agentic Toolkit

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

Press Release

Siemens accelerates integrated circuit design and verification with agentic AI in Questa One

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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