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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

Floating-Point Units (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

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July 2020 - Volume 16 Issue 2 (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

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VA Live 2023 - Huntsville (7)

Verification Complete (7)

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XML (7)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

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June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

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March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

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Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

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Visualization (6)

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YAML (6)

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ATPG (5)

Advance Your Verification Methodology (5)

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DAC 2024 (5)

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December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Scaling (5)

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February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

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March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

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Quirky (5)

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VA Live 2019 - Westford (5)

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IEEE (4)

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Non-Pipelined (4)

Non-Reset (4)

November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

Partitioning (4)

Phase Objections (4)

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UART (4)

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UPF 4.0 (4)

USB (4)

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Unreachability (4)

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VA Live 2023 - Austin (4)

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1.2 (3)

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Golden Model (3)

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Handles (3)

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Horizontal Reuse (3)

IC Design (3)

Integrity Challenges (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathematical Analysis (3)

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NRRs (3)

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Observer (3)

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PCI-SIG (3)

PHY (3)

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Phase-Level (3)

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Power Architecture (3)

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Profiling (3)

Protocol Layers (3)

QEMU (3)

QFL (3)

Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

RTL Sign-Off (3)

Radiation Mitigation (3)

Re-Spins (3)

Re-targeting (3)

Real Number Modeling (3)

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Routines (3)

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Singleton (3)

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Stream (3)

TBX (3)

TDISP (3)

Test Coverage (3)

Test Realization (3)

Transfer Protocols (3)

Transitive (3)

Trust Verification (3)

Type Casting (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

UVMC 2.3.2 (3)

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Unidirectional (3)

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VA Live 2026 - El Segundo (3)

VHDL-2019 (3)

VIP - 3.1 (3)

VbyOne (3)

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IEEE 754 (2)

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JTAG (2)

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Logic Cone (2)

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MBSE (2)

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Makefile (2)

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Memory Blocks (2)

Memory-based Sequences (2)

Metric Analyzers (2)

Multi-Clock Designs (2)

Multi-Language Environment (2)

Network ID Mapping (2)

Noise Reduction (2)

On-Chip (2)

OnChip (2)

Open Bus Interface (2)

PAM4 (2)

Packet Transfer (2)

Parameter-to-Signal (2)

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March 2021

Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar pdf
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation
Low Power Mar 31, 2021 Abdul Moyeen pdf
Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation
Low Power Mar 31, 2021 Abdul Moyeen pdf
I Didn’t Know Visualizer Could Do That
Debug Mar 30, 2021 Rich Edelman Webinar
Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing Mar 26, 2021 Ping Yeung Webinar
Applying Big Data to Next-Generation Coverage Analysis and Closure
Coverage Mar 26, 2021 Tom Fitzpatrick Conference
Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing Mar 26, 2021 Ping Yeung pdf
Applying Big Data to Next-Generation Coverage Analysis and Closure
Verification Management Mar 26, 2021 Darron May pdf
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich Webinar
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich pdf
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich pdf
Preventing Glitch Nightmares on CDC Paths: The Three Witches
Clock-Domain Crossing Mar 26, 2021 pdf
Preventing Glitch Nightmares on CDC Paths: The Three Witches
Clock-Domain Crossing Mar 26, 2021 pdf
ModelSim to Questa: Productivity Features
FPGA Verification Mar 25, 2021 Jonathan Craft Webinar
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi Webinar
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi pdf
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi pdf
Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Ping Yeung pdf
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Mark Eslinger Webinar
Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Ping Yeung pdf
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara pdf
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara Webinar
Cocotb Bus Functional Models
Python Mar 22, 2021 Ray Salemi link
Automatic Formal Verification - Questa Static and Formal Apps
Formal Verification Mar 21, 2021 Walter Gude Webinar
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Formal Verification Mar 18, 2021 Joon Hong Webinar

BUGGED OUT Podcast

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March 2021

Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip

Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation

Bringing Reset and Power Domains Together: Confronting Issues Due to UPF Instrumentation

I Didn’t Know Visualizer Could Do That

Preventing Glitch Nightmares on CDC Paths

Applying Big Data to Next-Generation Coverage Analysis and Closure

Preventing Glitch Nightmares on CDC Paths

Applying Big Data to Next-Generation Coverage Analysis and Closure

The Life of a SystemVerilog Variable

The Life of a SystemVerilog Variable

The Life of a SystemVerilog Variable

Preventing Glitch Nightmares on CDC Paths: The Three Witches

Preventing Glitch Nightmares on CDC Paths: The Three Witches

ModelSim to Questa: Productivity Features

Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Verification Learns a New Language: An IEEE 1800.2 Python Implementation

Spiral Refinement Methodology for Silicon Bug Hunt

Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt

Spiral Refinement Methodology for Silicon Bug Hunt

Advance your Designs with Advances in CDC and RDC

Advance your Designs with Advances in CDC and RDC

Cocotb Bus Functional Models

Automatic Formal Verification - Questa Static and Formal Apps

How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself