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March 2016 - Volume 12 Issue 1 (14)

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September 2021 - Volume 17 Issue 2 (12)

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June 2012 - Volume 8 Issue 2 (9)

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February 2013 - Volume 9 Issue 1 (8)

HDL Domain (8)

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June 2016 - Volume 12 Issue 2 (8)

March 2021 - Volume 17 Issue 1 (8)

Messaging (8)

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UCIe 2.0 (8)

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Israel Static & Formal Tech Day (7)

July 2020 - Volume 16 Issue 2 (7)

LLMs (7)

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March 2015 - Volume 11 Issue 1 (7)

March 2022 - Volume 18 Issue 1 (7)

March 2023 - Volume 19 Issue 1 (7)

Migration (7)

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November 2014 - Volume 10 Issue 3 (7)

November 2015 - Volume 11 Issue 3 (7)

Objections (7)

Order Property Pattern (7)

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VA Live 2023 - Huntsville (7)

Verification Complete (7)

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XML (7)

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Appendix (6)

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DAC 2018 (6)

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December 2017 - Volume 13 Issue 3 (6)

December 2022 - Volume 18 Issue 3 (6)

Design Constraints (6)

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HDL (6)

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IP Integration (6)

June 2019 - Volume 15 Issue 2 (6)

MARLUG 2023 (6)

MBIST (6)

MIPI (6)

March 2014 - Volume 10 Issue 1 (6)

March 2017 - Volume 13 Issue 1 (6)

March 2020 - Volume 16 Issue 1 (6)

March 2024 - Volume 20 Issue 1 (6)

Metric Validation (6)

November 2016 - Volume 12 Issue 3 (6)

November 2020 - Volume 16 Issue 3 (6)

October 2012 - Volume 8 Issue 3 (6)

October 2013 - Volume 9 Issue 3 (6)

Open Source (6)

PCIe Gen 7 (6)

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Pre-Silicon (6)

Random Faults (6)

Respins (6)

Slave (6)

Static & Formal Adoption (6)

Transaction-Level (6)

UCIe 3.0 (6)

UVM Forum (6)

UVVM (6)

VA Live 2024 - El Segundo (6)

VA Live 2024 - San Diego (6)

VA Live 2025 - El Segundo (6)

VA Live 2025 - Hudson (6)

VA Live 2025 - Huntsville (6)

VHDL Testbench (6)

Verbosity (6)

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Visualization (6)

Windows (6)

X-Effects (6)

YAML (6)

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ATPG (5)

Advance Your Verification Methodology (5)

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Constraint Solver (5)

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DAC 2024 (5)

DSP (5)

Data Encryption (5)

Debug Methodology (5)

December 2019 - Volume 15 Issue 3 (5)

Defect Coverage (5)

Design Scaling (5)

Dual Domains (5)

Error (5)

FMEDA (5)

February 2019 - Volume 15 Issue 1 (5)

Formal Testbench (5)

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High-Speed (5)

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March 2018 - Volume 14 Issue 1 (5)

Memory Usage (5)

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Quirky (5)

Repository (5)

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VA Live 2019 - Westford (5)

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C++ (4)

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IEEE (4)

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Non-Pipelined (4)

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November 2018 - Volume 14 Issue 3 (4)

PCIe Gen 6 (4)

Partitioning (4)

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Plusargs (4)

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UART (4)

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UPF 4.0 (4)

USB (4)

Unified Coverage Database (4)

Unreachability (4)

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VA Live 2023 - Austin (4)

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1.2 (3)

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Golden Model (3)

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Horizontal Reuse (3)

IC Design (3)

Integrity Challenges (3)

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JUnit (3)

July 2023 - Volume 19 Issue 2 (3)

Jump Statements (3)

LRM (3)

Level-shifter (3)

Load Balancing (3)

Loggers (3)

MC2 (3)

Mailboxes (3)

Mathematical Analysis (3)

Memory Debug (3)

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OSVVM (3)

Observer (3)

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PCI-SIG (3)

PHY (3)

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Phase-Level (3)

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Power Architecture (3)

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Profiling (3)

Protocol Layers (3)

QEMU (3)

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Qrun (3)

Quality Assurance (3)

RISC-V Verification Interface (3)

RTL Emulation (3)

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Re-Spins (3)

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Real Number Modeling (3)

Reconfiguration (3)

Resource Utilization (3)

Routines (3)

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Semiconductor (3)

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Stream (3)

TBX (3)

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Transfer Protocols (3)

Transitive (3)

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Type Casting (3)

UVM 1.1d (3)

UVM 1.2 (3)

UVM Rapid Adoption (3)

UVMC 2.3.0 (3)

UVMC 2.3.1 (3)

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Unreachable Code (3)

VHDL-2019 (3)

VIP - 3.1 (3)

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X-State (3)

2D/3D (2)

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IEEE 754 (2)

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MBSE (2)

MUX (2)

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Makefile (2)

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Metric Analyzers (2)

Multi-Clock Designs (2)

Multi-Language Environment (2)

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On-Chip (2)

OnChip (2)

Open Bus Interface (2)

PAM4 (2)

PMHF (2)

Packet Transfer (2)

Parameter-to-Signal (2)

Partitioned Compile (2)

Pattern Splitting (2)

Physical Layer (2)

Pipe Interface (2)

Point-to-Point Connections (2)

Power Constraints (2)

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March 2021

Applying Big Data to Next-Generation Coverage Analysis and Closure
Coverage Mar 26, 2021 Tom Fitzpatrick Conference
Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing Mar 26, 2021 Ping Yeung pdf
Applying Big Data to Next-Generation Coverage Analysis and Closure
Verification Management Mar 26, 2021 Darron May pdf
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich Webinar
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich pdf
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich pdf
Preventing Glitch Nightmares on CDC Paths: The Three Witches
Clock-Domain Crossing Mar 26, 2021 pdf
Preventing Glitch Nightmares on CDC Paths: The Three Witches
Clock-Domain Crossing Mar 26, 2021 pdf
ModelSim to Questa: Productivity Features
FPGA Verification Mar 25, 2021 Jonathan Craft Webinar
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi Webinar
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi pdf
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi pdf
Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Ping Yeung pdf
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Mark Eslinger Webinar
Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Ping Yeung pdf
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara pdf
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara Webinar
Cocotb Bus Functional Models
Python Mar 22, 2021 Ray Salemi link
Automatic Formal Verification - Questa Static and Formal Apps
Formal Verification Mar 21, 2021 Walter Gude Webinar
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Formal Verification Mar 18, 2021 Joon Hong Webinar
Practical Flows for Continuous Integration: Making the Most of Your EDA Tools
Questa Design Solutions Mar 16, 2021 Neil Johnson Webinar
Introduction to Coroutines
Python Mar 11, 2021 Ray Salemi link
Celebrating 10 Years of the UVM
UVM - Universal Verification Methodology Mar 03, 2021 Mark Peryer Article
Purging CXL Cache Coherency Dilemmas
Verification IP Mar 03, 2021 Nikhil Jain, Gaurav Manocha - Siemens Eda Article
What is “Verification” in the Context of DO-254 (Avionics) Programs?
Functional Safety Mar 03, 2021 Michelle Lange, Jeff Reeve And Tammy Reeve - Patmos Engineering Services Article

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

VA Live El Segundo

Tuesday, Feb 24th-9:30 AM PST

Discussing the latest advancements in RTL simulation.

FPU Verification Webinar

Wednesday, Feb 25th-8:00 AM PST

AI Assisted FPU Verification Using Questa One SFV

DVCon US 2026

March 2nd – 5th, 2026 | Hyatt Regency, Santa Clara

Verification IP Webinar

Wednesday, Mar 11th-8:00 AM PDT

Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

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Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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March 2021