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Solutions

The Verification Academy Solutions section delivers focused insights into key market segments and verification products that address today’s emerging challenges. Explore how advanced technologies and methodologies—spanning functional verification, safety, security, and more—are applied to solve real-world design problems. This curated content brings together best practices, expert perspectives, and proven tools to accelerate verification success.
Techniques

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Techniques

Design for Test Verification

Safety & Security

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Methodology

Unified Coverage

Design for Test Verification

Accelerating DFT Sign-Off with Questa One

Tackling Emerging DFT Verification Challenges with Questa One

Functional Safety

Functional Safety for ISO 26262

Functional Safety for DO-254

Unified Coverage

Questa One Unified Coverage Solution: Transforming Verification Through Intelligence

Boost Your Verification Productivity with Questa Verification IQ

Coverage Closure Acceleration Using Collaborative Verification IQ Tool

Functional Safety for ISO 26262

Accelerated Assurance with Questa One Functional Safety

Functional Safety for DO-254

Introduction to DO-254
Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
UVM

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Questa Design Solutions

Clock-Domain Crossing

Formal Verification

Reset-Domain Crossing

Verification Management & IP

Verification IQ

Verification IP

Verification Planning
Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
UVM

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UVM

UVM Basics

UVM Testbench

UVM Configuring a Test Environment

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UVM Stimulus Techniques

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UVM Debugging

UVM Connect

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UVM Coding

UVM Performance

UVM 1800.2

UVM 1.2

OVM to UVM

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UVM 1.2

UVM 1.1d

UVM 1.1c

UVM 1.1b

UVM 1.1a

Coverage

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Verification Horizons Blog

From Rule-Based Beginnings to AI-Driven Design: Tracing the Evolution of AI in EDA

DFT Verification: Tackling the Evolving Challenges

Closing the Gap in Software Skills for Verification Engineers

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Got Coverage?

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Events & Webinars

Siemens EDA at DAC 2025

Siemens EDA Forum Seoul 2025

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osmosis

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Debug

Faster Debug of Complex Testbenches using Visualizer

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Prevent Performance Problems with Prompt RTL Profiling

Accelerate Development Using Advanced Debugging Approaches

Formal Verification

Generating SystemVerilog Assertion (SVA) Properties with Property Assist

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Explore How to Protect Against Data Corruption with Formal Security Verification

Questa Formal Verification IP AMBA: Achieve Protocol Compliance in Designs

Functional Verification Workflow for Trusted and Assured Microelectronics

FPGA Verification

Securing your FPGA Design from RTL through to the Bitstream

Improving FPGA Safety and Security Compliance: FPGA Equivalence Checking from RTL to the Bitstream

Bringing Model-based Systems Engineering to IC and FPGA Design

ModelSim to Questa - Productivity Features

Functional Safety

Enhancing Automotive Safety Verification Using Questa One Sim FX

Enhancing Defect Coverage in DFT

Safety Analysis for Automotive Chips Based on ISO 26262

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Union of SoC Design & Functional Safety FlowUnion of SoC Design & Functional Safety Flow

Questa Design Solutions

Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Continuous Integration (CI) Driving Efficient Program Execution

Questa Design Solutions as a Sleep Aid

Applying Machine Learning to Accelerate CDC Analysis

Formal and the Next Normal

Questa Lint vs Formal AutoCheck

Simulation

Accelerating Functional Coverage with Questa One CX

Tackling Emerging DFT Verification Challenges with Questa One

Faster Debug Using QuestaSim Interactive Coverage Analysis

Unlocking the Power of QuestaSim and Visualizer Integration

Productivity in the Questa Simulation Flow

SystemVerilog

Introduction to SystemVerilog Assertions

Generating SVA Properties with Property Assist

Easy Test Writing with a Proxy-driven Testbench

Making Your DPI-C Interface a Fast River of Data

The Life of a SystemVerilog Variable

Verification IP

Breaking Barriers: Ethernet 1.6T, Infiniband, UALink, and UEC Verification for Next-Gen Connectivity

PCIe Gen7 Verification with Siemens Avery Verification IP

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

The Future of Multi-Die System Verification with UCIe

Verification IQ

Streamlining Requirements Traceability using Questa Verification IQ Testplan Author

Smart Debug: Accelerate Root Cause Analysis and Reduce Debug Turnaround Time with Questa Verification IQ Regression Navigator

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

Boost Your Verification Productivity with Questa Verification IQ

Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data

Verification Planning

Solving the Semiconductor Verification Crisis: From Problem to Productivity

Functional Verification Study - 2022

The Three Pillars of Intent-Focused Insight

Trends in Functional Verification

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March 2021

Purging CXL Cache Coherency Dilemmas
Verification IP Mar 03, 2021 Nikhil Jain, Gaurav Manocha - Siemens Eda Article

October 2020

Arasan MIPI® CSI-2-RX IP Verification Using Questa Verification IPs
Verification IP Oct 26, 2020 Vikas Sharma - Siemens Eda Article
Unified Approach to Verify Complex FSM
Verification IP Oct 26, 2020 Milan Patel - Einfochips, Ltd (An Arrow Company) Article

May 2020

Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP
Verification IP May 28, 2020 Munish Goyal Webinar

December 2019

Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing Dec 03, 2019 Kurt Takara Article

April 2019

Don’t Do It Yourself: Questa VIP Accelerates UVM Testbench Development
Verification IP Apr 09, 2019 Tom Fitzpatrick pdf

June 2018

Coverage Driven Verification of NVMe Using Questa VIP (QVIP)
Verification IP Jun 29, 2018 Anurag Singh - Siemens Eda Article

March 2018

SATA Specification 3.3 Gaps Filled by SATA QVIP
Verification IP Mar 01, 2018 Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens Eda Article

February 2018

Agents: Architecture and Operation
UVM Framework Feb 26, 2018 Bob Oden pdf
Agents: Architecture and Operation
UVM Framework Feb 26, 2018 Bob Oden Session

June 2017

MIPI® CSI2 TX IP Verification Using Questa Verification IPs
Verification IP Jun 28, 2017 Ivan Ristic Article
Enterprise Ethernet PHY Verification
Verification IP Jun 13, 2017 Akshay Sarup Seminar
Trends and Requirements in High Speed Interface Verification
Verification IP Jun 13, 2017 Niraj Mathur Seminar
MIPI® CSI-2 TX Verification
Verification IP Jun 13, 2017 Ivan Ristic Seminar
Leveraging the latest DDR & Flash Memory Models
Verification IP Jun 13, 2017 Jason Polychronopoulos Seminar

December 2016

Five Common Pitfalls To Avoid While Verifying PCIe® Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma Paper
Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers
Verification IP Dec 19, 2016 Saurabh Sharma pdf
Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Dec 19, 2016 Saumya Agrawal pdf
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara Webinar
What Is CDC Protocol Verification, Prevent Bugs in Your Silicon
Clock-Domain Crossing Dec 05, 2016 Kurt Takara pdf

June 2016

Simplifying HDCP Verification Using Questa Verification IP
Verification IP Jun 01, 2016 Raman Jain, Priya Minocha - Siemens Eda Article

March 2016

Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 12, 2016 Saumya Agrawal - Siemens Eda Paper
Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Verification IP Mar 02, 2016 Saumya Agrawal - Siemens Eda Article
Nine Effective Features of NVMe® Questa Verification IP to Help You Verify PCIe® Based SSD Storage
Verification IP Mar 02, 2016 Saurabh Sharma - Siemens Eda Article
MIPI C-PHY™: Man of the Hour
Verification IP Mar 02, 2016 Yogesh Chaudhary - Siemens Eda Article

51–75 of 93

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