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Vectors (2)

Verification Crisis (2)

Verification Cycles (2)

Vertical Reuse (2)

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March 2022

Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article
UVVM – VHDL Verification Methodology for Faster and Better FPGA and ASIC Verification
VHDL 2008 Mar 02, 2022 Espen Tallaksen - Emlogic Article

February 2022

Equivalence Checking for FPGA
Formal Verification Feb 25, 2022 Martin Rowe Webinar
Achieving High Defect Coverage for Safety Critical and High Reliability Designs
Functional Safety Feb 22, 2022 Lee Harrison Webinar
‘The Dog Ate my RTL’ Doesn’t Work Anymore
Questa Design Solutions Feb 15, 2022 Joe Hupcey Webinar
‘The Dog Ate my RTL’ Doesn’t Work Anymore
Questa Design Solutions Feb 15, 2022 Joe Hupcey pdf
Guidelines to a Successful ISO 26262 Lifecycle
Functional Safety Feb 04, 2022 Jacob Wiltgen link

January 2022

Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee pdf
Introduction to Questa Lint and CDC for Designers
Questa Design Solutions Jan 25, 2022 Mathew Yee Webinar
Odds and Ends
Python Jan 14, 2022 Ray Salemi link

December 2021

Logging in PYUVM
Python Dec 14, 2021 Ray Salemi link
Courtines and COCOTB Testbench Code
Python Dec 14, 2021 Ray Salemi link
Exhaustive Trust & Security Verification by Leveraging Emerging Standards
Formal Verification Dec 08, 2021 John Hallman mp4
Exhaustive Trust & Security Verification by Leveraging Emerging Standards
Formal Verification Dec 08, 2021 John Hallman pdf

November 2021

Validation of Complex Safety Architectures
Functional Safety Nov 18, 2021 Vedant Garg Webinar
The UVM Factory
Python Nov 17, 2021 Ray Salemi link
How Do You Qualify Tools for DO-254
Functional Safety Nov 14, 2021 Michelle Lange, Tammy Reeve - Patmos Engineering Services pdf
How Do You Qualify Tools for DO-254
Functional Safety Nov 14, 2021 Michelle Lange, Tammy Reeve - Patmos Engineering Services Paper
Formal 101: Data Independence and Non-Determinism Made Easy
Formal Verification Nov 11, 2021 Jin Hou Session
Data Independence and Non-Determinism Made Easy
Formal Verification Nov 11, 2021 pdf
How to Finish Faster with Hierarchical CDC+RDC Methodologies
Questa Design Solutions Nov 02, 2021 Kurt Takara pdf
Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies
Questa Design Solutions Nov 02, 2021 Kurt Takara Webinar

October 2021

The Configuration Database in PYUVM
Python Oct 27, 2021 Ray Salemi link
Improving Your SystemVerilog Language and UVM Methodology Skills
SystemVerilog Oct 27, 2021 Chris Spear Track

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

UALink VIP Webinar

Wednesday, Oct 15th-10:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

DVCon Europe 2025

October 14th - 15th | Munich, Germany

osmosis Europe 2025

October 16th | Munich, Germany

RISC-V Summit 2025

October 22nd - 23rd | Santa Clara, CA

Simulation Webinar

Thursday, Oct 23rd-8:00 AM PDT

Improving Verification Productivity Using Questa One Sim

Portable Stimulus Webinar

Wednesday, Oct 29th-10:00 AM PDT

Portable Stimulus: What can it do for me? | Presented by Doulos

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

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