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July 2023 - Volume 19 Issue 2 (3)

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June 2017 - Volume 13 Issue 2 (2)

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May 2021

Using the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Using the Register Layer
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
Register-Based Testing
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick Session
Register-Based Testing
UVM - Universal Verification Methodology May 25, 2021 Tom Fitzpatrick pdf
The Three Witches Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing May 18, 2021 Ping Yeung pdf
Machine Learning at the Edge: Using HLS to Optimize Power and Performance
Machine Learning May 12, 2021 Michael Fingeroff - Siemens Eda pdf
Formal 101 – Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 Mark Eslinger Session
Setting Up & Optimizing Constraints
Formal Verification May 10, 2021 pdf
Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Functional Safety May 04, 2021 Jacob Wiltgen Webinar

April 2021

Low Power Considerations for Verification
Low Power Apr 29, 2021 Rick Koster Webinar
Formal 101 – Basic Abstraction Techniques
Formal Verification Apr 21, 2021 Jin Hou Session
A Methodology for Comprehensive CDC+RDC Analysis
Clock-Domain Crossing Apr 20, 2021 Kurt Takara pdf
A Methodology for Comprehensive CDC+RDC Analysis
Clock-Domain Crossing Apr 20, 2021 Kurt Takara Webinar
A Guide to QVIP Workflow and Debug for PCIe®
Verification IP Apr 08, 2021 Akshay Sarup Webinar
Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 link
Generic SCSI-Based Host Controller Verification Framework Using SystemVerilog
Verification IP Mar 31, 2021 pdf
Early Design Validation AI Accelerator’s System Level Performance Using An HLS Design Methodology
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda pdf
Early Design & Validation of an AI Accelerator’s Performance Using an HLS Design
High-Level Synthesis Mar 31, 2021 Michael Fingeroff - Siemens Eda Seminar
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Making Your DPI-C Interface a Fast River of Data
SystemVerilog Mar 31, 2021 Rich Edelman Webinar
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar Webinar
Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Bringing Reset and Power Domains Together – Confronting UPF Instrumentation
Low Power Mar 31, 2021 Abdul Moyeen Webinar
Making Your DPI-C Interface A Fast River Of Data
SystemVerilog Mar 31, 2021 Rich Edelman pdf

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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