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Formal Verification Sep 28, 2021 pdf
Improving Initial RTL Quality
Questa Design Solutions Sep 15, 2021 Chris Giles Webinar
Improving Initial RTL Quality | Japanese
Questa Design Solutions Sep 15, 2021 Chris Giles pdf
Improving Initial RTL Quality
Questa Design Solutions Sep 15, 2021 Chris Giles pdf
Questa AutoCheck - Advanced Linting
Questa Design Solutions Sep 14, 2021 Mark Eslinger Demo
Questa X-Check: Identify "X" Issues
Formal Verification Sep 14, 2021 Mark Eslinger Demo
Questa Lint - Find and Fix RTL Issues
Questa Design Solutions Sep 14, 2021 Tom Carlstedt-Duke Demo
Questa CDC Verification
Questa Design Solutions Sep 14, 2021 Kurt Takara Demo
Python and the UVM
Python Sep 09, 2021 Ray Salemi link
Questa Reset Domain Crossing (RDC)
Reset-Domain Crossing Sep 02, 2021 Atul Sharma Demo
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You
Formal Verification Sep 01, 2021 Tom Fitzpatrick Article
Digital Thread, Digital Twin, and IC Development
Functional Safety Sep 01, 2021 Ray Salemi Article
Addressing the Trends and Challenges of Automotive IC Development
Functional Safety Sep 01, 2021 Ann Keffer Article
Deploying HLS in a DO-254/ED-80 Workflow
Functional Safety Sep 01, 2021 Tammy Reeve - Patmos Engineering Services Article
Hardware-Assisted Verification Through the Years
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive
Acceleration Sep 01, 2021 Jean-Marie Brunet Article
Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs
Acceleration Sep 01, 2021 Stephen Bailey Article
"Hug the Debug" – Before It’s Too Late
Debug Sep 01, 2021 Sumit Vishwakarma Article
Questa Visualizer Adds Coverage Analysis to the Platform
Debug Sep 01, 2021 Yara Esam - Siemens Eda Article
Verifying a DDR5 Memory Subsystem
Verification IP Sep 01, 2021 Kamlesh Mulchandani Article
Expediting Simulation Turn-around Time with Incremental Build Flow
Simulation Sep 01, 2021 Neil Johnson Article
Standards Participation at Siemens EDA
Standards Sep 01, 2021 Dave Rich Article

August 2021

IP Security: Keys to Early Identification of Security Vulnerabilities
Formal Verification Aug 27, 2021 John Hallman Webinar
UVM Connect 2.3 Primer
UVMC Aug 25, 2021 John Stickley pdf
RDC Overview & Questa RDC Methodology
Reset-Domain Crossing Aug 21, 2021 Atul Sharma Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag Tcl/Tk

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