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March 2022

Confidently Sign-off any Low-Power Designs without Consequences
Low Power Mar 23, 2022 pdf
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger pdf
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger pdf
How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage
Formal Verification Mar 23, 2022 Mark Eslinger mp4
UVM-AMS - An Update on the Accellera UVM
UVM - Universal Verification Methodology Mar 23, 2022 pdf
Estimating Power Dissipation of End-User Application on RTL
Low Power Mar 23, 2022 pdf
UVM-AMS - An Update on the Accellera UVM
UVM - Universal Verification Methodology Mar 23, 2022 mp4
Modeling Analog Devices using SV-RNM
Analog Mixed-Signal Mar 23, 2022 mp4
Path-based UPF Strategies Optimally Manage Power on your Designs
Low Power Mar 23, 2022 pdf
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Video)
UVMC Mar 23, 2022 Vishal Baskar mp4
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Paper)
UVMC Mar 23, 2022 Vishal Baskar pdf
Why not “Connect” using UVM Connect: Mixed Language communication got easier with UVMC (Poster)
UVMC Mar 23, 2022 Vishal Baskar pdf
Formal 101 - Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 Joe Hupcey Webinar
Fast, Scalable Formal Verification Made Easy
Formal Verification Mar 17, 2022 pdf
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
Questa Design Solutions Mar 10, 2022 Buu Huynh pdf
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster
Questa Design Solutions Mar 10, 2022 Buu Huynh Webinar
UVM Framework Release 2022.1
UVM Framework Mar 09, 2022 Bob Oden tar
Verification of HPC Protocols and Memories
Verification IP Mar 08, 2022 Gordon Allan Webinar
Verification of HPC Protocols and Memories
Verification IP Mar 08, 2022 Gordon Allan pdf
NVMe-oF – Simple, Invisible Fabric to Cloud Storage
Verification IP Mar 02, 2022 Dhruv Garg - Siemens Eda Article
Getting to Know Visualizer - Part I
Debug Mar 02, 2022 Rich Edelman Article
Enabling Model-Based Design for DO-254 Certification Compliance
Functional Safety Mar 02, 2022 Jacob Wiltgen Article
How Do You “Qualify” Tools for DO-254 Programs?
Functional Safety Mar 02, 2022 Michelle Lange, Tammy Reeve - Patmos Engineering Services Article
Reflections on Users’ Experiences with SVA
SystemVerilog Mar 02, 2022 Ben Cohen Article
A Faster Approach to Co-Simulation Using Questa and VPI
Simulation Mar 02, 2022 Vicente Bergas, Andrew Robertson, Marco Denicolai - Bitec Article

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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