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July 2021

Traceability for Automotive Standards Compliance
Functional Safety Jul 29, 2021 Darron May Webinar
The Future of Automotive and its Impact on Safety
Functional Safety Jul 29, 2021 Ann Keffer Webinar
Part II: Verification of PCIe® IP
Verification IP Jul 15, 2021 Stephane Hauradou Webinar
Equivalence Checking for FPGA
Formal Verification Jul 06, 2021 Martin Rowe Webinar

June 2021

Leveraging Advancements in UPF 3.1 for Effective Design and Verification
Low Power Jun 23, 2021 Gabriel Chidolue Webinar
Part I: Introduction to PCIe® Gen 6
Verification IP Jun 08, 2021 Gordon Allan Webinar

May 2021

Optimizing a Fault Campaign for Complex Mixed-Signal Devices
Functional Safety May 04, 2021 Jake Wiltgen Webinar

April 2021

Low Power Considerations for Verification
Low Power Apr 29, 2021 Rick Koster Webinar
A Methodology for Comprehensive CDC+RDC Analysis
Reset-Domain Crossing Apr 20, 2021 Kurt Takara Webinar
Easy Test Writing with a Proxy-driven Testbench
SystemVerilog Apr 06, 2021 Ray Salemi Webinar

March 2021

Functional Debug: Verification and Beyond
Debug Mar 31, 2021 Hanan Moller Webinar
Making Your DPI-C Interface a Fast River of Data
SystemVerilog Mar 31, 2021 Rich Edelman Webinar
Primary, Anonymous, or What? The Destiny of Ports from Design Top from Off-Chip
Low Power Mar 31, 2021 Progyna Khondkar Webinar
“Bounded Proof” Sign-Off with Formal Coverage
Formal Verification Mar 31, 2021 Joe Hupcey Webinar
I Didn’t Know Visualizer Could Do That
Debug Mar 30, 2021 Rich Edelman Webinar
Preventing Glitch Nightmares on CDC Paths
Clock-Domain Crossing Mar 26, 2021 Ping Yeung Webinar
The Life of a SystemVerilog Variable
SystemVerilog Mar 26, 2021 Dave Rich Webinar
ModelSim to Questa: Productivity Features
FPGA Verification Mar 25, 2021 Jonathan Craft Webinar
Verification Learns a New Language: An IEEE 1800.2 Python Implementation
Python Mar 25, 2021 Ray Salemi Webinar
Formal Verification Experiences: Spiral Refinement Methodology for Silicon Bug Hunt
Formal Verification Mar 24, 2021 Mark Eslinger Webinar
Advance your Designs with Advances in CDC and RDC
Questa Design Solutions Mar 23, 2021 Kurt Takara Webinar
Automatic Formal Verification - Questa Static and Formal Apps
Formal Verification Mar 21, 2021 Walter Gude Webinar
How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Formal Verification Mar 18, 2021 Joon Hong Webinar
Practical Flows for Continuous Integration: Making the Most of Your EDA Tools
Questa Design Solutions Mar 16, 2021 Neil Johnson Webinar
Trends in Functional Verification
Planning, Measurement and Analysis Mar 02, 2021 Harry Foster Webinar

BUGGED OUT Podcast

Every chip has bugs — the real question is how fast you can find and fix them.

VA Live El Segundo

Tuesday, Feb 24th-9:30 AM PST

Discussing the latest advancements in RTL simulation.

FPU Verification Webinar

Wednesday, Feb 25th-8:00 AM PST

AI Assisted FPU Verification Using Questa One SFV

DVCon US 2026

March 2nd – 5th, 2026 | Hyatt Regency, Santa Clara

Verification IP Webinar

Wednesday, Mar 11th-8:00 AM PDT

Shift-Left Compute Subsystem RTL Sign-Off with Software Aware VIP

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

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