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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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December 2017 - Volume 13 Issue 3 (3)

Design Constraints (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

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October 2012 - Volume 8 Issue 3 (3)

Parallel Simulation (3)

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UVMC 2.3.3 (3)

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VA Live 2019 - Westford (3)

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December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

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June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

LVS (2)

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March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metric Validation (2)

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October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

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DRAM (1)

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EMC (1)

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Elliptic Curve (1)

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Emerging Trends (1)

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Execution Trace (1)

FPGA Development (1)

Factory (1)

February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

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Flash (1)

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Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

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March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Marvell (1)

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NAND (1)

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Non-Resettable Registers (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

Observer (1)

PCIe Gen 4 (1)

Partitioned Compile (1)

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Windows (1)

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XML (1)

YAML (1)

eFuse (1)

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February 2013

Boost Verification Results by Bridging the Hardware/Software Testbench Gap
UVM - Universal Verification Methodology Feb 27, 2013 Matthew Ballance Paper
Register Verification: Do We Have Reliable Specification?
Formal Verification Feb 27, 2013 Wesley Park - Siemens Eda Paper
Register Verification: Do We Have Reliable Specification?
Formal Verification Feb 27, 2013 Wesley Park - Siemens Eda pdf
Boost Verification Results by Bridging the Hardware/Software Testbench Gap
UVM - Universal Verification Methodology Feb 27, 2013 Matthew Ballance pdf
Transaction-Level Friending: Connecting TLM Models in SystemC and SystemVerilog
UVMC Feb 27, 2013 Adam Erickson pdf
The Formal Verification of Design Constraints
Formal Verification Feb 25, 2013 Ajay Daga - Fishtail Design Automation Article

January 2013

VHDL-2008 Overview
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Testbench Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
RTL Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Operator Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Package Type Enhancements
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Fixed Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session
Floating Point Package
VHDL 2008 Jan 18, 2013 Jim Lewis Session

October 2012

ST-Ericsson Speeds Time to Functional Verification Closure with Questa
Verification IQ Oct 01, 2012 Rachida El Idrissi - St-Ericsson Article
The Top Five Formal Verification Applications
Formal Verification Oct 01, 2012 Roger Sabbagh - Siemens Eda Article
Evolution of UPF: Getting Better All the Time
Low Power Oct 01, 2012 Erich Marschner Article

September 2012

UVM Connect 2.2 Kit
UVMC Sep 07, 2012 John Stickley tar

August 2012

Applied Assertions
FPGA Verification Aug 30, 2012 Ray Salemi Session
Transactions
FPGA Verification Aug 30, 2012 Ray Salemi Session

June 2012

Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs
FPGA Verification Jun 15, 2012 Stephan Van Beek, Sudhir Sharma, Sudeepa Prakash - Mathworks Article
Introduction to Metrics
Planning, Measurement and Analysis Jun 01, 2012 Harry Foster Session
The Driving Forces for Change
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What Can Metrics Tell Us?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What's Needed to Address the Problem?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session
What's Needed to Adopt Metrics?
Planning, Measurement and Analysis Jun 01, 2012 Andreas Meyer Session