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March 2016 - Volume 12 Issue 1 (5)

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March 2015 - Volume 11 Issue 1 (4)

March 2024 - Volume 20 Issue 1 (4)

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VA Live 2023 - Austin (4)

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December 2017 - Volume 13 Issue 3 (3)

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July 2022 - Volume 18 Issue 2 (3)

June 2015 - Volume 11 Issue 2 (3)

March 2020 - Volume 16 Issue 1 (3)

March 2021 - Volume 17 Issue 1 (3)

Memory Models (3)

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October 2012 - Volume 8 Issue 3 (3)

Parallel Simulation (3)

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UPF 4.0 (3)

UVMC 2.3.3 (3)

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VA Live 2019 - Westford (3)

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Variable (3)

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2.5D (2)

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December 2019 - Volume 15 Issue 3 (2)

December 2022 - Volume 18 Issue 3 (2)

Design Checking (2)

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IEEE (2)

IEEE 754 (2)

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ISA (2)

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Jittering (2)

June 2013 - Volume 9 Issue 2 (2)

June 2014 - Volume 10 Issue 2 (2)

Lockstep (2)

Loggers (2)

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Machine Readable Specification (2)

March 2014 - Volume 10 Issue 1 (2)

March 2017 - Volume 13 Issue 1 (2)

March 2022 - Volume 18 Issue 1 (2)

Metastable (2)

Metric Validation (2)

Mixed-Signal Design (2)

Modules (2)

Monitor (2)

NVM Express (2)

Non-Determinism (2)

Object Oriented Programming (2)

October 2013 - Volume 9 Issue 3 (2)

OnChip (2)

Open Architecture (2)

PAM4 (2)

PCI-SIG (2)

PCIe Gen 7 (2)

PMHF (2)

Parameter (2)

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SFV (2)

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Scoreboard (2)

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Shift Left (2)

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Spice (2)

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UALink (2)

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USB (2)

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UVMC 2.3.1 (2)

UVMC 2.3.2 (2)

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VRM (2)

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osmosis 2024 A&D (2)

$display (1)

3PIP (1)

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Factory (1)

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February 2013 - Volume 9 Issue 1 (1)

February 2019 - Volume 15 Issue 1 (1)

Fibre Channel (1)

Flash (1)

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GPU (1)

Generation (1)

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Japanese (1)

July 2020 - Volume 16 Issue 2 (1)

July 2023 - Volume 19 Issue 2 (1)

June 2012 - Volume 8 Issue 2 (1)

June 2016 - Volume 12 Issue 2 (1)

June 2017 - Volume 13 Issue 2 (1)

June 2018 - Volume 14 Issue 2 (1)

June 2019 - Volume 15 Issue 2 (1)

LSTM (1)

Logic Faults (1)

Low Latency (1)

MCPs (1)

MUX (1)

March 2018 - Volume 14 Issue 1 (1)

March 2023 - Volume 19 Issue 1 (1)

Mathworks (1)

Memory BIST (1)

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NAND (1)

NLP (1)

Namespaces (1)

Non-Trivial Bug Escapes (1)

November 2015 - Volume 11 Issue 3 (1)

November 2016 - Volume 12 Issue 3 (1)

November 2018 - Volume 14 Issue 3 (1)

November 2020 - Volume 16 Issue 3 (1)

OSCI (1)

Objectives (1)

Objects (1)

Observer (1)

PCIe Gen 4 (1)

PHY (1)

Partitioned Compile (1)

Phases (1)

Phrase Configuration (1)

Power Gating (1)

Pre-Silicon (1)

Productivity Gap (1)

Property Analysis (1)

Property Editor (1)

Prototyping (1)

QOS Processor (1)

RAM (1)

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RDMA (1)

RISC-V Verification Interface (1)

RNG (1)

RTL Emulation (1)

RTL-Aware Design (1)

Re-Spins (1)

Receiver (1)

Recording (1)

Recurrent Neural Networks (1)

Release Notes (1)

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Reset Handling (1)

Reset Tree (1)

Respins (1)

Root Complex (1)

Run Monitor (1)

SATA (1)

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SOTIF (1)

SPDM (1)

SPI (1)

SSD (1)

SafeSPI (1)

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Scenario Generation (1)

Security Protocol and Data Model (1)

Sequencer (1)

Sequential Optimization (1)

Signal Processing Domain (1)

Single Root-IO Virtualization (1)

Singleton (1)

Softmodel (1)

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Specification Driven Formal (1)

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Static CDC (1)

Strategy (1)

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Subscriber (1)

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System Level (1)

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TBX (1)

TPU (1)

Tcl/Tk (1)

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Transactors (1)

Transmitter IP (1)

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UCIS (1)

UEC (1)

UPF 3.1 (1)

USB 3.0 (1)

USB 3.1 (1)

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UVM-MS (1)

UVMC 2.1.4 (1)

UVMC 2.2 (1)

UVVM (1)

Ultra Accelerator Link (1)

Unary (1)

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Use Models (1)

VA Live 2023 - El Segundo (1)

VC File (1)

VCMs (1)

VIP - 3.1 (1)

Values (1)

Verbose (1)

Verbosity (1)

Verification Architecture (1)

Verification Component (1)

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Virtual Equivalence (1)

Virtual Methods (1)

WRG (1)

Wall-Clock Run-Time (1)

X-Optimism (1)

XML (1)

YAML (1)

eFuse (1)

Show Less

December 2019

Deadlock Prevention Made Easy with Formal Verification
Formal Verification Dec 03, 2019 Dr. Jeremy Levitt Article
Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon
Clock-Domain Crossing Dec 03, 2019 Kurt Takara Article

November 2019

UVM Connect 2.3.2 Kit
UVMC Nov 14, 2019 John Stickley tar
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf
UVM Connect 2.3.2 HTML
UVMC Nov 14, 2019 John Stickley tar
UVM Connect 2.3.2 Primer
UVMC Nov 14, 2019 John Stickley pdf

October 2019

Questa PropCheck GUI - Overview
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Cone of Influence
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Debug a Firing
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Properties Tab
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Property Editor
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Run Monitor/Details
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Schematic
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Source Window
Formal Verification Oct 10, 2019 Mark Eslinger Demo
Questa PropCheck GUI - Run Formal
Formal Verification Oct 10, 2019 Mark Eslinger Demo

September 2019

Questa SLEC Fact Sheet
Formal Verification Sep 30, 2019 Nicolae Tusinschi link

August 2019

Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
A New Approach to Low Power Verification: Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava Paper

July 2019

Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick Conference
Portable Stimulus: Is It Revolution or Evolution?
Portable Stimulus Jul 15, 2019 Tom Fitzpatrick pdf
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide Conference
Tessent: DFT Enablement for AI Devices
Machine Learning Jul 15, 2019 Geir Eide pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf

New White Papers!

Formal, Avery VIP, Coverage, UPF, Functional Safety and More!

User2User Mid-Atlantic 2025

Nov. 19th | 0800 - 1630 US/Eastern

Johns Hopkins University | Laurel, Maryland

osmosis Europe 2025

Thursday, October 16th, 2025 - Munich, DE

DV Digest on YouTube

AI is Changing Verification | Interview with Abhi Kolpekwar

Verification IP Webinar

Wednesday, Oct 15th-8:00 AM PDT

Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery VIP

QuestaSim Webinar

Wednesday, Oct 01st-8:00 AM PDT

Did You Know QuestaSim Supports VHDL-2019?

Questa Developer Webinar

Wednesday, Oct 08th-8:00 AM PDT

Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

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