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December 2022 - Volume 18 Issue 3 (4)

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June 2019 - Volume 15 Issue 2 (4)

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February 2019 - Volume 15 Issue 1 (3)

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March 2017 - Volume 13 Issue 1 (3)

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December 2019 - Volume 15 Issue 3 (2)

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April 2019

Block level testbench
UVM - Universal Verification Methodology Apr 02, 2019 tar

March 2019

Five Steps to Quality CDC Verification
Clock-Domain Crossing Mar 13, 2019 Ping Yeung pdf

February 2019

Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich Paper
Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Rohit Jain Paper
UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman Paper
Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Questa Design Solutions Feb 28, 2019 Rohit Jain pdf
UVM IEEE Shiny Object
UVM - Universal Verification Methodology Feb 28, 2019 Rich Edelman pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich pdf
The Missing Link: The Testbench to DUT Connection
SystemVerilog Feb 28, 2019 Dave Rich Paper
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung pdf
Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Clock-Domain Crossing Feb 28, 2019 Ping Yeung Paper
Clock-Domain Crossing (CDC) Challenges in Latch Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara pdf
Clock-Domain Crossing (CDC) Challenges in Latch-Based Designs
Clock-Domain Crossing Feb 28, 2019 Kurt Takara Paper
Low Power Apps: Shaping the Future of Low Power Verification
Low Power Feb 28, 2019 pdf
Using Strong Types in SystemVerilog Design and Verification Environments
SystemVerilog Feb 28, 2019 Dave Rich pdf
Formal Apps Take the Bias Out of Functional Verification
Formal Verification Feb 25, 2019 Bill Au Article
Simplifying Assertion Validation Using UVM Callbacks
Assertions Feb 25, 2019 Arushi Jain - Siemens Eda Article
Selecting a Portable Stimulus Application Focal Point
Portable Stimulus Feb 25, 2019 Matthew Ballance Article
Choosing a Format for the Portable Stimulus Specification
Portable Stimulus Feb 22, 2019 Matthew Ballance pdf

January 2019

Accelerating Verification through Verification IP, Configurator and UVM Framework
Verification IP Jan 24, 2019 Sharath Kannareddy pdf
Making Verification Fun Again
UVM Framework Jan 24, 2019 Jonathan Craft pdf
Welcome & Overview
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf
ASIC & FPGA SoC Functional Verification Trends
Planning, Measurement and Analysis Jan 24, 2019 Harry Foster pdf

December 2018

Full-Featured SOC Debug Cross-Triggering
Simulation Dec 10, 2018 Verification Methodology Team Article

November 2018

FPGA Verification Challenges and Opportunities
FPGA Verification Nov 28, 2018 Harry Foster Article

Verification IP Webinar

Wednesday, May 20th-8:00 AM PDT

Breaking Bandwidth Barriers in the AI Era: Scaling PCIe with Retimers and Optical Innovation

VA Live BRNO - Czech Republic

Thursday, May 21st | 9:00 AM - 3:15 PM CEST

The seminar will highlight recent advances in Questa One and the growing role of AI in verification workflows.

Security Verification Webinar

Wednesday, Jun 03rd-8:00 AM PDT

AI for Early SoC Security Verification

BUGGED OUT Podcast

Episode #4: Harry Foster talks with Vladislav Palfy about coverage closure.

DVCon Keynote

Beyond Bigger Designs: Rethinking Verification for the Era of Convergence

DVCon Workshop

Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

New White Papers

Agentic AI, Avery VIP, Coverage, Formal Verification, Functional Safety, UPF and More!

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