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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
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      • SystemVerilog Testbench Acceleration
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      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
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      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

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  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
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      • Bus Protocol Coverage
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • September 2021
  • Questa Visualizer Adds Coverage Analysis to the Platform

Questa Visualizer Adds Coverage Analysis to the Platform

Verification Horizons - Tom Fitzpatrick, Editor

| Verification Horizons - September 2021 by Yara Esam, Siemens EDA

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INTRODUCTION

Questa Visualizer Debug is our high performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs. Visualizer recently introduced new functionality for coverage support giving the user many ways to analyze and improve coverage closure with ease. Starting with Coverage gives you another way to diagnose problems, Visualizer provides great improvement to the coverage data representation, taking advantage of its existing rich visualization capabilities. It is built with improved capacity and performance to

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Table of Contents

Verification Horizons Articles:

  • Good Things Come in Pairs, Including Acquisitions and Digital Twins!

  • Technologist Interview: What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You

  • Digital Thread, Digital Twin, And IC Development

  • Addressing the Trends and Challenges of Automotive IC Development

  • Deploying HLS in a DO-254/ED-80 Workflow

  • Hardware-Assisted Verification Through the Years

  • Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive

  • Veloce Prototyping Solutions Accelerate Verification of HPC AI-Enabled SoCs

  • "Hug the Debug" – Before It’s Too Late

  • Questa Visualizer Adds Coverage Analysis to the Platform

  • Verifying a DDR5 Memory Subsystem

  • Expediting Simulation Turn-around Time with Incremental Build Flow

  • Standards Participation at Siemens EDA

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