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"We've enjoyed sharing so many articles about verification techniques and technology with you over the years, we look forward to continuing that mission."
—Tom Fitzpatrick
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Welcome to the 10th Anniversary edition of Verification Horizons! It's hard to believe we've been doing this long enough to reach such a significant milestone, but it's been a great ride. For me personally, this issue marks two significant milestones as well.
My son and I reached the pinnacle of our Boy Scout experience this past summer when we successfully completed a 10-day 80-mile hike at the Philmont Scout Ranch in New Mexico, including reaching the 12,441 ft. summit of Baldy Mountain. Please indulge me in a bit of fatherly pride when I tell you that the highlight of the trip was sharing the experience with my son. The other major milestone is that my daughter has just started high school.
She's quickly gotten involved in the Drama Club and was cast in the fall play, which is a milestone I'm sure she'll remember for a long time. We are very proud of how well she's handled this transition in her life, despite the fact that it makes my wife and me feel old that our youngest is now in high school.
As with everything, milestones mark the end of one phase and the beginning of another. As much as we've enjoyed sharing so many articles about verification techniques and technology with you over the years, we look forward to continuing that mission as we advance to our next milestone. So, we begin this issue with "Memories Are Made Like This" by my colleague Mark Peryer of our Verification IP group.
This article explains how the new Model Generator utility in our Questa® VIP (QVIP) library can be used to generate DDR and LPDDR models that match the behavior of over 750 commercially available memory devices. The easy-to-use graphical utility lets you specify the device you want and creates a wrapper module around the Mentor DDR QVIP BFM to provide an accurate and sophisticated simulation model to support your verification effort.
In "A New Stimulus Model for CPU Instruction Sets," my colleagues Staffan Berg and Mike Andrews show how to create a portable stimulus model to verify that a specific implementation of a processor is fully compliant with the specification. Using a graph lets you describe the entire instruction set more concisely and efficiently than relying on SystemVerilog constraints, and by being at a higher level of abstraction also allows multiple implementations to be derived from a single description. Some of the work being done in the Accellera Portable Stimulus Working Group is building on these concepts.
We next take a look at post-silicon debug in "On-Chip Debug – Reducing Overall ASIC Development Schedule Risk" by my colleague Eric Rentschler. If you've ever wondered how to see what's happening inside an FPGA or ASIC and how to debug the kinds of "long-latency" bugs that may slip through simulation, this article is for you. You'll learn how our Certus™ debug solution automates the creation of debug infrastructure in your design and provides visibility and analysis capability that feels just like your simulation-based debug environment.
Our friend Lauro Rizzatti next brings us up-to-date in the finale of his three-part series "Hardware Emulation: Three Decades of Evolution." In this installment, we see how emulation grew to where it is now used to debug hardware and develop software in parallel. This exhaustive case study will hopefully provide you with a solid foundation to help you decide how to incorporate emulation into your next verification project, if you haven't already.
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In our Partners' Corner this issue, we begin with our friends at Agnisys who explain how "QVIP Provides Thoroughness in Verification." This article is a great case study of the benefits in using Questa VIP to reliably verify many different configurations of AMBA® slave modules generated by their iDesignSpec TM tool. Most importantly, it allowed them to prove to their customers that their generated design IP is compliant with the standard.
Next, our friends at Oski Technology present "Minimizing Constraints to Debug Vacuous Proofs," which explains how to improve formal verification productivity by isolating a minimal set of constraints necessary to identify failures and eliminate false positive results. If you're using formal verification and running into this problem, you should definitely take a look.
We conclude this issue with our friends at SyoSil Aps discussing "A Generic UVM Scoreboard." Those of you who use UVM are no doubt aware that the basic scoreboard component in the standard library is of limited usefulness. For cases where you need a more robust and scalable scoreboard, this article will explain how theirs works, and how you can download and use it on your next project.
I'd like to take this opportunity to thank Rebecca Granquist, who is really the "wizard behind the curtain" for Verification Horizons. She has made my job as Editor so much easier over the years and is a huge part of whatever success we've achieved. Looking back on the last ten years, I can honestly say that, professionally, it really doesn't seem that long. When you have a job that you enjoy, as they say, time really does fly.
Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons
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