Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and micro-architectural feature has been exercised. Typical approaches involve collecting large test-suites of real SW, as well as using program generators based on constrained- random generation of instruction streams, but there are drawbacks to each.
SystemVerilog Constrained-Random (CR) 'single class with constraints on all possible fields approach' can be unwieldy and hard for solvers to handle, especially when dealing with a series of instructions with many for each constraint. Slow solving