One of the most common requirements for the verification of a chip, board or system is to be able to model the behaviour of memory components, and this is why memory models are one of the most prevalent types of Verification IP (VIP).
Figure 1. Memory model functionality
Memory models have two main functions. The first is to store information in a data structure so that it can be written, retrieved and updated. The second is to provide a signal level interface which allows access to the storage array using a pre-defined protocol (see figure 1 for a representative functional block diagram). For effective verification the model should also check that the signal level protocol from the host interface is behaving correctly, provide a backdoor access to the storage