INTRODUCTION
One of the most common requirements for the verification of a chip, board or system is to be able to model the behaviour of memory components, and this is why memory models are one of the most prevalent types of Verification IP (VIP).
Figure 1. Memory model functionality
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Memory models have two main functions. The first is to store information in a data structure so that it can be written, retrieved and updated. The second is to provide a signal level interface which allows access to the storage array using a pre-defined protocol (see figure 1 for a representative functional block diagram). For effective verification the model should also check that the signal level protocol from the host interface is behaving correctly, provide a backdoor access to the storage array and provide a means of collecting functional coverage.
Over the years, memory devices such as Dynamic RAMs (DRAM) have driven semiconductor process development as manufacturers have sought to create faster memories with a greater storage capacity through the use of smaller feature sizes. Over time, several different memory protocols have been developed to optimise the various trade-offs between device access speed and packaging costs, and today, one of the most widely used protocols is the Double Data Rate (DDR) memory protocol, and its low power variant, LPDDR. The DDR protocol is designed for high speed access, with data being transferred on both edges of the clock. However, in practice, this high level of throughput can only be achieved by managing the DDR accesses so that the time and power expensive operations such as activate and pre-charge can be taking place in one part of the memory whilst a data transfer takes place with another part of the memory. It is the task of a DDR controller to order the operations taking place in the DDR device to maximise throughput, and in order to verify the complex trade-offs a sophisticated memory model is needed.
In order to address the need for accurate DDR models, the Model Generator utility was introduced in the 10.4b release of Mentor’s Questa VIP (QVIP) library. The function of the Model Generator is to generate DDR and LPDDR models that match the behaviour of commercially available memory parts.
MODEL GENERATOR
QVIP Model Generator is an easy to use graphical utility that allows a user to specify and create a DDR or LPDDR model that will match the behaviour of over 750 commercially available devices. Underlying Model Generator is a code generator that supports all types of DDR and LPDDR models as defined in the JEDEC JESD79 and JESD209 specifications, with all possible configurations of device width, density and speed. The models are generated based on a memory manufacturer’s part number that represents an entry in a database that contains the details of each target memory device. The generated model is implemented as a Verilog module that is wrapped around the Mentor DDR QVIP.
To create a part in Model Generator GUI, the user first has to choose the DDR type and the manufacturer, this narrows their search down to a list of available devices. Then the user selects the required device from those part numbers available in the reduced list and then they press the generate button to write out the code for the device model. Figure 2, shows a screen shot of the part number selection pane for Micron DDR3 memories, the table entry row in blue is the one that has been selected. Table 1 lists the memory devices available from the various memory vendors that are supported by Model Generator.
The Model Generator software allows the user to create several models in a session, and also to specify the name of the generated model.
GENERATED MEMORY MODELS
The DDR/LPDDR models generated by Model Generator are intended to be instantiated in a VHDL, Verilog or SystemVerilog/UVM testbench module as a component module. The models are reactive, in other words, they respond to the signalling on the protocol wires in order to determine how to behave and do not require any user stimulus in order to provide their functionality.
The models have a port map that corresponds to the memory device selected, and in some cases the models have several DDR/LPDDR interfaces since the selected memory device package contains several die. Each type of DDR and LPDDR has a different pin interface, and depending on the protocol there are several data bus width options per device, some of which have a further influence over the pin out. The generator has built-in rules that ensure that the right pin out is used. Most of the signal pins are simple inputs or outputs, but the data pins and their strobes are bidirectional, and the model switches between driving or receiving on these pins according to the current mode of operation.
Table 1. Available memory device types by manufacturer
| DDR Manufacturer |
DDR2 |
DDR3 |
DDR4 |
LPDDR2 |
LPDDR3 |
LPDDR4 |
|---|
| Micron |
Available |
Available |
Available |
Available |
Available |
Available |
| Samsung |
NA |
Available |
Available |
Available |
Available |
NA |
| SK-Hynix |
NA |
Available |
Available |
Available |
Available |
NA |
| ESMT |
Available |
Available |
NA |
NA |
NA |
NA |
| ETRON |
Available |
Available |
NA |
NA |
NA |
NA |
Figure 2. Screen shot of the Model Generator GUI
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Figure 3. Model Generator memory model functional diagram
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The models are wrapped around the DDR QVIP BFM – see figure 3 for a functional block diagram of the features of the Model Generator memory model. The DDR QVIP BFM is configured by code inside the module to provide the correct functionality for the part selected in the generator. In addition to modelling the behaviour of the DDR memory, the QVIP BFM also has built-in assertions for protocol violations and will report any errors that occur.
TRANSACTIONAL FEATURES
The generated models support two additional features that are normally only available in the context of UVM testbenches – functional coverage and transaction reporting. The functional coverage monitor is enabled by setting the models ENABLE_FUNC_COV parameter to a ‘1’. The functional coverage is collected by taking advantage of the transaction recognition features of the DDR QVIP BFM. Enabling the functional coverage monitor gives users of VHDL and Verilog testbenches the opportunity to take advantage of the built-in functional coverage to check which aspects of DDR or LPDDR functionality they have tested with their stimulus. The transaction reporting function is enabled by setting the models ENABLE_TXN_LISTENER parameter to a ‘1’. The transaction reporter prints a record to the transcript every time a transfer takes place over the DDR interface. Both of these features need to be enabled by the user, since they are disabled by default to optimise simulation performance.
The default behaviour of the models is that they are configured to work in the absence of a UVM testbench. If the NO_UVM parameter is set to ‘0’, then the functional coverage monitor and the transaction logger participate in the UVM phases. There is no support for creating a DDR memory agent in a UVM env since the DDR BFM needs no active stimulus.
Another transactional feature built into the models is the ability to use the hierarchical transaction viewing feature of the DDR QVIP to debug DDR activity via the Questa waveform view – see figure 4 for an example. This feature takes advantage of the built-in transactional objects that are available across the QVIP library.
Figure 4. Screen shot of DDR QVIP transactions
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BACKDOOR API
The models also support a backdoor API which enables the memory data storage array to be accessed directly without using the DDR signal interface. The backdoor API is intended to allow the user to either pre-load areas of memory with data, or to examine stored data content. The available API calls are summarised in table 2, and can be called using a hierarchical reference to the memory model. There are several applications for this back door access functionality. If the design under test (DUT) contains one or more processors, then the DDR would provide the storage for the software binaries and the backdoor write API would be used to transfer a copy into the memory model. If the design contains a DMA function, then an area of memory would be initialised through the back door write API with a block of data containing a signature that would be copied to other places in memory during the course of the test case. Another possibility could be that the DUT has a data processing function, in which case the DDR memory would be initialised with the starting data on which the design would perform a transform and then write the result to another area of memory. The backdoor write APIs take an address and an array of bytes as their arguments. The data array content is written to consecutive locations starting at the given address.
Table 2. Model Generator backdoor API summary
| Backdoor API Call Summary |
|---|
| backdoor_wr_by_address(address, data[]); |
| backdoor_wr_by_brc(bank, row, column, data[]); |
| backdoor_rd_by_address(address, length, data[]); |
| backdoor_rd_by_brc(bank, row, column, length, data[]); |
| dump_memory_content(mem_data_content[]); |
Working in the opposite direction, the backdoor read APIs allow the content of the memory to be read back which can be useful for checking whether a data processing application has worked correctly, or that a known sequence of data transfers has completed successfully. The backdoor read APIs use a length argument to determine how many bytes are read back, starting from the location addressed by the address argument.
Finally, the dump_memory_content() API allows the DDR model to report on all locations accessed during the course of the simulation, listing bank, row and column addresses together with data content.
CONCLUSION
The Model Generator utility, released as part of the QVIP 10.4b library, supports models for more than 750 DDR and LPDDR commercial memory devices. The generated models provide comprehensive verification support for DDR and LPDDR memory interfaces, with a pin level interface, a complete set of protocol checking assertions, a functional coverage monitor and transaction reporting.
Model Generator proves an easy (EZ) way to generate an accurate and sophisticated simulation model for a standard part that can quickly be integrated into any Verilog or VHDL testbench.
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