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INTRODUCTION
With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions. In the pre-silicon world, there exists a great opportunity for a solution that can provide more cycles of execution than what is possible today with simulation and emulation. But in the past, functions like power management span HW, FW, BIOS, virtualization and OS levels and are difficult to cover until silicon hardware is available. The most recent industry tape-out data shows that despite
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