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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

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      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  • Home
  • Verification Horizons
  • March 2023
  • Democratizing digital-centric mixed-signal verification methodologies

Democratizing digital-centric mixed-signal verification methodologies

Verification Horizons - Tom Fitzpatrick, Editor

by Sumit Vishwakarma - Siemens EDA

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As the world of technology continues to evolve, the way we design and verify circuits is also evolving. The next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern System-on-Chips (SoCs). Mixed-signal designs are a combination of tightly interwoven analog and digital circuitry. There are two main reasons for increased mixed-signal contents in today's SoC.

Firstly, machines today are consuming more and more real-world analog information, such as light, touch, sound, vibration, pressure, or temperature, and bringing it into the digital world for processing. Secondly, technology scaling is enabling integration of more functionality, increased

...

Table of Contents

Verification Horizons Articles:

  • Everything, everywhere, all at once: Big data reimagines verification predictability and efficiency

  • Democratizing digital-centric mixed-signal verification methodologies

  • Lane margining at receiver and its application through pipe message bus

  • The RISC-V Verification Interface (RVVI) – test infrastructure and methodology guidelines

  • A formal-based approach for efficient RISC-V processor verification

  • Jumpstart your formal verification with a little help

  • Resolving metastability issues for multi-clock SOC environment for I2C

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