Multi-Die System Verification with Siemens’s UCIe VIP
In this session, we will introduce you to Siemens EDA's Verification Portfolio and then deep dive into UCIe Verification IP, discussing its key features such as dynamic block-level and SoC level testbench creation, traffic generation, error injection, debug features, and performance monitoring. Siemens Avery UCIe Verification IP is a leading solution in the market, runs on all major simulators and is a native SystemVerilog/UVM class-based Verification IP.
Full-access members only
Register your account to view Multi-Die System Verification with Siemens’s UCIe VIP
Full-access members gain access to our free tools and training, including our full library of articles, recorded sessions, seminars, papers, learning tracks, in-depth verification cookbooks, and more.