Verification Academy Live: Silicon Valley

Agenda

9:30 AM – 10:00 AM

• Registration and Check-in
  • Coffee and networking with your peers

10:00 AM – 10:05 AM

• Welcome and Introductions
  • Nidhi Jain | AE Manager, Functional Verification

10:05 AM– 10:45 AM

• Keynote: Accelerated Confidence: Revolutionizing Chip Development with Next-Gen Verification IP
  • Abhi Kolpekwar | VP & GM, Digital Verification Technologies Division

10:45 AM – 11:20 AM

• Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration
  • Luis Rodriguez | Engineering Site Lead

Chiplet-based architectures are revolutionizing SoC design, overcoming power, performance, and area bottlenecks. The Universal Chiplet Interconnect Express (UCIe) standard enables seamless, high-performance chiplet integration with optimized power and latency. UCIe 2.0 enables a management layer and the ability to create management fabric and complex domain topologies.

This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.

11:20 AM - 11:55 AM

• Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity
  • Pankaj Goel | Associate R&D Director

As data-intensive applications such as AI, 5G, and high-performance computing drive the need for faster and more reliable networks, Ethernet technology is evolving to unprecedented speeds. This session introduces Avery Verification IP for Ethernet 1.6T, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.

We will also cover UALink and UEC solutions, which address pressing requirements in ultra-high-speed communication links and unified Ethernet controller architectures. We will demonstrate how Avery's Verification IP enables faster time-to-market by ensuring compliance with industry standards, interoperability, and functional correctness.

Noon – 1:00 PM

• Lunch and Networking

1:00 PM - 1:35 PM

• Accelerating Innovation: PCIe Gen7 Verification for High-Speed Design
  • Zhihong Zeng | Verification IP Architect
  • Jalaj Gupta | Product Engineer

With PCIe Gen 7 pushing the boundaries of data transfer speeds to 128 GT/s, alongside PAM4 signaling and advanced power management, ensuring robust and efficient design verification has become paramount. Avery PCIe Verification IP offers a powerful, comprehensive solution for validating PCIe Gen 7 designs, while ensuring backward compatibility with earlier PCIe generations.

This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring your designs meet the demands of next-generation PCIe applications.

1:35 PM - 2:10 PM

• Bridging SoC HW/SW: Co-simulation Challenges and Solutions for X86, ARM, RISC-V Based SoC Teams
  • Chris Browy | Verification IP Architect

Chip design teams and Firmware/Software design teams that we work with seek concurrent engineering, verification and validation approaches that add productivity, reduce project risk, add first-silicon quality, and meet time-to-market goals. They are building and verifying SoCs involving Compute Subsystem IP such as ARM Neoverse CSS or RISC-V ecosystem IP solutions from SiFive and others. Many of these designs are peripherals that integrate into host platforms using advanced protocol interfaces such as PCIe, CXL, Ethernet, and next generation standards such as UA Link and others.

The challenges include a need for early verification of all the interfaces around those subsystems in a simulation while both hardware and software are still under development - needing integrated simulation across multiple abstraction levels, detailed coverage with real world system level stimulus/workloads and low power scenarios, productive debug sessions, and fast turnaround time. All of this is needed before we move to full SoC system-level verification using hardware accelerated solutions.

The Avery VIP team have created solutions in this space that can mix abstraction levels and software as stimulus for our SoC subsystem testbenches. We'll demonstrate how you can benefit from fast, productive verification, while in the simulation phase of your project, with our available Virtual In-Circuit Simulation VIP solutions.

2:10 PM - 2:45 PM

• Next-Gen Memory Unlocked: HBM4 and LPDDR6 Verification for High-Performance Computing
  • Kamlesh Mulchandani | Applications Engineering Consultant
  • Martin Chang | Product Engineer

High Bandwidth Memory (HBM) has transformed AI, machine learning, and high-performance computing by addressing data transfer bottlenecks and boosting performance. The upcoming HBM4 standard takes this further, offering unprecedented speeds to support faster AI model training and execution. Similarly, LPDDR6, the next-generation Low Power Double Data Rate memory, sets a new benchmark with its advanced features, including increased data rates, enhanced power efficiency, and innovative error correction mechanisms.

In this session, discover how Siemens’ Avery Verification IP for HBM4 and LPDDR6 provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how our leading users leverage this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications.

2:45 PM- 3:30 PM

• Ask the Experts Panel and Closing Remarks

** SEATING IS LIMITED, register below to save your seat.

Date & Time

Thursday, January 30th
9:30 AM - 3:30 PM

Location

Siemens EDA
46871 Bayside Parkway, Building B
Fremont, CA, 94538
+1 (510) 354-7400

<sup><sub>PLEASE NOTE:
- Building B will show the address 46885 above the entry door (this is the correct building).
- This event is in-person only -- there is no support for remote participation.</sub></sup>