Siemens EDA at GOMACTech

March 17th - 20th, 2025 | Pasadena Convention Center

View Sessions!

New Master’s-level Course

Functional Verification of Digital Logic

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IC/ASIC & FPGA Trends

2024 Siemens EDA and Wilson Research Group Functional Verification Study

Now Available!

Debug Webinar

Faster Debug of Complex Testbenches Using Visualizer

Now Available!

ISO 26262 Webinar

Wednesday, Mar 12th-8:00 AM PDT

Safety Analysis for Automotive Chips Based on ISO 26262

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Safety & Security Webinar

FPGA Equivalence Checking from RTL to the Bitstream

On-Demand
SIEMENS Verification Academy

Verification Academy Live: Silicon Valley

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

This seminar will show how to leverage next-gen verification IP to rapidly verify high-performance protocol designs being employed on today's 3DICs and SoCs.

Joe Hupcey

  1. Post-Event Archive

    • VA Live - Silicon Valley: Introduction and Welcome

      VA Live Jan 30, 2025 Nidhi Jain - Siemens Eda pdf

      Welcome to Verification Academy Live.

    • Mastering UCIe 2.0 Verification: Ensuring Seamless Chiplet Integration

      Verification IP Jan 30, 2025 Luis Rodriguez pdf

      This session will focus on the Siemens Avery UCIe Verification IP and the new UCIe2.0 features. Discover its capabilities in dynamic environment creation, including generating complex SiP topologies, portable traffic generation, error injection, and debugging all within a native SystemVerilog/UVM framework.

    • Breaking Barriers: Ethernet 1.6T, UALink, and UEC Verification for Next-Gen Connectivity

      Verification IP Jan 30, 2025 Pankaj Goel - Siemens Eda pdf

      This session introduces Avery Verification IP for Ethernet 1.6T, UALink, and UEC, providing essential tools to verify complex designs for next-generation connectivity. You will gain insights into the key challenges and innovations in Ethernet 1.6T, the latest high-speed Ethernet standard, and learn how Avery's Verification IP accelerates design validation with comprehensive protocol coverage, scalability, and advanced debugging capabilities.

    • Accelerating Innovation: PCIe Gen7 Verification for High-Speed Design

      Verification IP Jan 30, 2025 Zhihong Zeng, Jalaj Gupta - Siemens Eda pdf

      This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks. Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring designs meet demands of next-generation PCIe applications. Guest Speaker: Ganesh Venkatakrishnan from Scaleflux presented his experience with the Avery PCIe VIP.

    • Bridging SoC HW/SW: Co-simulation Challenges and Solutions for X86, ARM, RISC-V Based SoC Teams

      Verification IP Jan 30, 2025 Chris Browy pdf

      The Avery VIP team have created solutions in this space that can mix abstraction levels and software as stimulus for our SoC subsystem testbenches. We'll demonstrate how you can benefit from fast, productive verification, while in the simulation phase of your project, with our available Virtual In-Circuit Simulation VIP solutions.

    • Next-Gen Memory Unlocked: HBM4 and LPDDR6 Verification for High-Performance Computing

      Verification IP Jan 30, 2025 Kamlesh Mulchandani pdf

      In this session, discover how Siemens’ Avery Verification IP for HBM4 and LPDDR6 provides a scalable and customizable solution for rigorous protocol compliance and performance testing. Learn how our leading users leverage this VIP to verify their memory controller IP and subsystems, ensuring reliability and readiness for next-generation applications. Guest Speaker: Nidish Kamath from Rambus spoke about Rambus's HBM4 memory controller and the partnership with Avery memory VIP.