Released on March 8th, 2022.
Didn’t get to go to DAC 58? Catch up on the best of DAC in this technical presentation, which was recorded at DAC, followed by a live Q&A session hosted by the presenters.
High Performance Compute architectures are changing, driven by three goals:
- Achieve the most favorable economics
- Provide the highest performance
- Leverage the advantage of AI/ML alongside traditional processors
To enable those goals, there are new interconnect protocols, memory solutions, and storage connectivity solutions at all levels of the datacenter, from chip through package, board, backplane, module, and rack to facility level. New solutions change the game for design and verification, and demand expertise and comprehensive support from EDA.
In this technical session we focus on the advances in PCI Express generation 6 protocol, and on the Compute Express Link (CXL) protocol.
What You Will Learn:
- Verification strategy for complete PCIe/CXL coverage
- Verifying interconnect security and integrity with IDE
- How interconnect meets memory, and productivity solutions to enable time-to-market
Who Should Attend:
- Verification Engineers & Managers and those interested in high performance protocols