Released on July 29th, 2021.
Overview:
Developing a testbench with complex Verification IP components is a monumental task taking up many weeks and multiple iterations in the verification cycle of a SoC development project. QVIP Configurator is a Graphical User Interface (GUI) based tool aimed at providing a jump start for building a complete ready-to-use testbench for Questa Verification IP with the ability to re-use components into an existing testbench.
This session walks through the step-by-step workflow to integrate Questa Verification IP (QVIP) – USB4 into a testbench. The workflow demonstrates a jump start guide on developing a complete working testbench using QVIP, thereby reducing the testbench development efforts, and also the efforts needed for integrating QVIP into an existing testbench.
Debugging a complex protocol like USB is a mammoth task and requires extensive protocol knowledge. If one doesn’t have the know-how it may take up many man hours to find the issue.
USB QVIP solution caters to both experienced and new verification engineers with robust USB QVIP offerings.
This session also includes the USB4 QVIP architecture and its various use models and built in stimulus. Along with this we will also uncover various debug mechanism that will enable to accurately pin point design related issue.
What You Will Learn:
- The workflow of integrating a Verification IP into a testbench
- Ease of use on developing a complete testbench using QVIP USB
- The debug capabilities of QVIP USB provides detailed visibility and record of transfers exchanged over the USB link
Who Should Attend:
Design & Verification Engineers & Managers and those developing complex testbenches for SoC Verification using standard Verification IP components
