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Update on Formal-based Trust and Security Verification Flows
Resource (Slides) - Jun 14, 2023 by John Hallman
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Securing RISC-V Military Projects
Resource (Slides) - Jun 14, 2023 by Christopher Diltz, Edaptive Computing, Inc.
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TSS SoC Sign-Off Methodology: Quality & Productivity Gains
Resource (Slides) - Jun 14, 2023 by Dr. Vasker Bhattacherjee - Edaptive Computing, Inc.
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Formal Verification of Security Properties
Resource (Slides) - Jun 14, 2023 by Ratish Punnoose - Sandia National Laboratories
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OneSpin EC-FPGA: Evolution and Updates
Resource (Slides) - Jun 14, 2023 by Kevin Urish
In this session, you will learn how OneSpin EC-FPGA accelerates the design flow and identifies bugs before they escape by enabling aggressive optimization usage.
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Siemens Government Technologies and Microelectronics Assurance
Resource (Slides) - Jun 14, 2023 by Justin Brisco - Siemens Government Technologies
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data
Resource (Slides) - Jun 06, 2023 by Austin Mam
This session will cover Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using analytics, collaboration, and traceability. VIQ utilizes machine learning to boost verification productivity, inspired by the collective feedback gathered from verification teams over many years.
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Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow
Resource (Slides) - Jun 06, 2023 by Walter Gude
In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.
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The New Leader in Verification IP: Questa + Avery Solutions
Resource (Slides) - Jun 06, 2023 by Gordon Allan
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the industry leader for Verification IP. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
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Revolutionizing RTL Design: Unveiling the Latest Updates and Roadmap of the Questa Simulation Platform
Resource (Slides) - Jun 06, 2023 by Moses Satyasekaran
During this session we will unveil our latest Questa Simulation platform updates, with a behind-the-scenes look at our strategic investments in expanding functionality, enhancing performance, and delivering more intuitive debug capabilities.
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Transactional Assertions - Where representation influences thinking
Resource (Slides) - May 31, 2023 by Nicolae Tusinschi
In this session, you will learn about more about transactional assertions.
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GapFree - Where all pieces come together
Resource (Slides) - May 31, 2023 by Nicolae Tusinschi
In this session, you will learn how OneSpin joining Siemens EDA creates a compelling combination by providing a comprehensive, best-in-class, accessible Formal solution.
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Break the RISC-V customization barrier with Processor Formal Verification
Resource (Slides) - May 31, 2023 by Salaheddin Hetalani
In this session, you will learn the challenges of processor verification and how the RISC-V community recognizes the need for stronger verification.
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When Regular CDC Is Not Enough: Reset Domain Crossing Verification and Hierarchical Data Modeling (HDM)
Resource (Slides) - May 31, 2023 by Kevin Campbell
In this session, you will learn more about RDC and how to accelerate your CDC with hierarchical data models.
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A multi-dimensional view of formal verification coverage
Resource (Slides) - May 31, 2023 by Nicolae Tusinschi
In this session, you will learn more about formal coverage and verification coverage integration advantages.
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Advanced CDC flows: Dynamic Metastability Modeling, Protocol Verification, Reconvergence
Resource (Slides) - May 31, 2023 by Kevin Campbell
In this session, you will learn more how dynamic CDC addresses static CDC limitations, and how to benefit from CDC transfer protocols and structural reconvergence verification.
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Enhancing CDC flows with Machine Learning (ML) today, and the future roadmap of static solutions
Resource (Slides) - May 31, 2023 by Kevin Campbell
In this session, you will learn why Siemens EDA is investing in the power of machine learning (ML) in static & formal verification to increase efficiency and confidence.
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osmosis Aerospace and Defense 2023
Conference - May 30, 2023 by Martin Rowe
osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
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Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?
Resource (Verification Horizons Blog) - May 24, 2023 by Rich Edelman
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this year – and anyhow, my wife is the gardener in the house. But it’s my job to do some weeding. While meditative, it is disagreeable to me. But back to UVM Debug and Visualizer.
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Efficient Interconnect Formal Verification for Complex, Large-scale Designs
Webinar - May 17, 2023 by Nicolae Tusinschi
In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
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Efficient Interconnect Formal Verification for Complex, Large-scale Designs
Resource (Slides) - May 17, 2023 by Nicolae Tusinschi
In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
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Delivering First Silicon Success for Your Next SoC or 3DIC
Resource (Slides) - Apr 25, 2023 by Gordon Allan
Now that our acquisition of Avery Design Systems is complete, Siemens EDA are the new leaders in Verification IP in the industry. Our combined team of experts are ready to provide the industry with a complete protocol and memory verification portfolio, to bring independent, high-quality verification, standards-based solutions that are interoperable across all simulators, and quality which is already trusted by the most successful silicon teams across the globe.
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Delivering First Silicon Success for Your Next SoC or 3DIC
Webinar - Apr 25, 2023 by Gordon Allan
In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.
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Groups of Class Specializations in SystemVerilog
Resource (Verification Horizons Blog) - Apr 25, 2023 by Chris Spear
In a previous post , I said that in SystemVerilog, once you specialize a class, you can not make a group of them. Oops! Turns out that UVM does this all this time. You just need to know where to start. Just to be clear, you are making a group of handles, an array. Every object is separate, and thus cannot organized into an array.
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data
Webinar - Apr 11, 2023 by Darron May
In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.