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Questa Verification IQ Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Verification IQ is implemented in a web-based application framework providing scalable verification management with zero install for device and OS independence. It supports public, private, and hybrid cloud configurations with native collaboration and centralized data access. Questa Verification IQ presents all tasks within a familiar, modern, user interface protected by a secure, login-based licensing model, and it supports URL sharing and user-based notification systems.
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Questa Signoff CDC Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Signoff CDC uses automated, advanced structural analysis algorithms optimized for gate-level analysis, as well as automated leveraging of waiver and CDC path information from Questa CDC RTL analysis for exacting, “low noise” results.
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Questa Visualizer Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago; for example, clocking requirements, security requirements, safety requirements, and requirements.
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Questa Verification IP Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Siemens EDA Questa® Verification IP (QVIP) integrates seamlessly into all advanced verification environments on any simulator. With a consistent and easy-to-use UVM architecture across all protocols, QVIP ensures maximum productivity and flexibility for the verification of block level, subsystem, and SoC designs.
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Exploring the Multifaceted Landscape of Formal Coverage
Webinar - Sep 20, 2023 by Nicolae Tusinschi
In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.
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UVM Framework Release 2023.3
Resource (Tarball) - Sep 08, 2023 by Bob Oden
General Updates: Testplan runnable in RMDB now griddable Validator updated to support ICVIP YAML fields Generator Updates: Initial integration for ICVIP 2023.3 dpi_define YAML structure supports C functions that have no arguments BCR Updates: Merge pragmas added to .compile files Deprecation notice: Deprecating qvip memory agents type allong with qvip_utils_pkg
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Digital Transformation: How Siemens EDA Helps You Engineer a Smarter Future Faster
Resource (Technical Paper) - Sep 02, 2023 by Mike Santarini - Siemens EDA
This pace of digital transformation will accelerate even more rapidly as more companies begin to incorporate artificial intelligence (AI) and machine learning (ML) into their systems to leverage and even monetize the exponentially increasing amount of data produced by seemingly “everything digital.” Siemens EDA is dedicated to helping more companies advance in their digital transformation and engineer a smarter future faster.
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Breaking the RISC-V Processor Customization Barrier with Formal Verification
Webinar - Jul 19, 2023 by Sven Beyer
In this session, you will learn the role that formal has in state-of-the-art processor DV and the QoS processor core verification workflow.
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Revolutionizing Circuit Design: Unveiling the latest updates and roadmap of Questa Simulation Tools
Resource (Slides) - Jun 22, 2023 by Moses Satyasekaran
Discover how our cutting-edge Questa Simulation tools revolutionize the industry and deliver users' best product experience. During this session, we will unveil our latest product updates and discuss our exciting investments in the future of our product roadmap. Plus, you'll get a behind-the-scenes look at our strategic investments in the product, including our plans for expanding functionality, enhancing performance, and delivering even greater value to our users.
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Third-Party IP Assurance Using AutoCheck
Resource (Slides) - Jun 22, 2023 by Luke Wolff - VeriSi Corporation
The use of Third-Party Intellectual Property (3PIP) in Aerospace and Defense (A&D) designs raises concerns about the level of trust that can be placed in 3PIP. In the absence of a full testbench with documentation what can be done to improve trust in 3PIP? Questa Formal AutoCheck provides an option for assessing designs with a low threshold for design comprehension. This presentation will explore the application of AutoFormal to 3PIP and provide examples of issues found in real 3PIP.
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Simple, Maintainable, Accessible, and Reusable Testplans
Resource (Slides) - Jun 22, 2023 by Toanl Nquyer - VeriSi Corporation
Testplans are a necessary step in the verification process but can be cumbersome depending on the user’s development environment. Available software may not be compatible with testplan plug-ins, and frustrating idiosyncrasies can arise during XML export. The YAML format is very similar to XML but is much more accessible and maintainable. This presentation discusses the benefits of using the YAML format as a base for testplan generation.
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Questa Verification IQ: Boost verification predictability and efficiency
Resource (Slides) - Jun 22, 2023 by Jonathan Stanley
Big Data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. In this session, you will learn how Siemens’s latest offering, Questa Verification IQ (VIQ), can help you accelerate coverage closure, better manage your test and compute resources, and provide overall faster verification turnaround times by using analytics, collaboration, and traceability.
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Debugging RTL and UVM in Post-sim and Live-sim in the Visualizer Debug Environment
Resource (Slides) - Jun 22, 2023 by Rich Edelman
The Visualizer Debug Environment is the debug framework for simulation, static, formal, emulation, prototyping, analog and more. Visualizer and the Questa QIS technology ensures the fastest simulation while logging and prevents mismatches between regression simulations and debug simulations. Visualizer raises the debug abstraction using the Transaction viewer, the FSM view, the logic cone and the schematic viewer. Complex UVM testbench can be debugged easily in the wave window.
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Continuous Integration (CI) / DevSecOps
Resource (Slides) - Jun 22, 2023 by Martin Rowe
Modern systems and products rely on complex microelectronic components now more than ever to monitor, control and process critical information. Due to their importance in the system or product, an exploit of these devices may result in a risk to personal safety, financial loss, exposure of personal information, and operation failure. Functional verification of microelectronic devices requires thorough methods and verifying that the ICs in the system are free of these exploits requires even more.
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Integrating the Value of Questa Design Solutions Into Your Continuous Integration (CI) Development Flow
Resource (Slides) - Jun 22, 2023 by Walter Gude
In this presentation, we will show how to automate the detection of hard-to-spot issues (e.g., CDC, FSM deadlock, combo loops, etc.) as early as possible in the design cycle with a continuous integration environment. In this flow, design quality is automatically checked at every code check-in and other scheduled intervals – which can reduce costs and drive predictable schedule execution.
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Whoops There Goes Another Config
Article - Jun 21, 2023 by Rich Edelman
This is all made up. Except the true parts. It’s a murder mystery. Someone “murdered” my config setting – but I’m getting ahead of the story. We’re verification engineers, and our testbench is running just fine, doing the things it does, but the system is running a bit slower than our System Architects predicted.
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Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project
Article - Jun 21, 2023 by Emin Akgün, Hilal Güneren - ANKASYS
In this article, we will discuss the Display Data Bus of ARINC-708. The bus plays a critical role in terms of the pilot’s point of view. It requires a bi-phase Manchester encoding and decoding. For both Manchester coding and the bus protocol, some examples of possible error types are considered.
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Mitigating System Failure Risks by verifying the Safeness of SafeSPI sub-module for the Automotive Industry
Article - Jun 21, 2023 by Gopi Srinivas Deepala, Himanshu Vishwakarma, Avnita Pal - Silicon Interfaces
This article outlines a systematic approach to attain safety objectives and create a conducive environment for achieving them. It includes a comprehensive inventory of alarms, faults, and their corresponding categories, all presented in a step-by-step format.
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Decoding LLM Hallucinations: Insights and Taming them for EDA Applications
Resource (Verification Horizons Blog) - Jun 15, 2023 by Dan Yu
In an earlier blog , I explained that LLM will learn much faster than humans and there are many possible applications in verification. Two months later, the latest iteration of ChatGPT has been passing many harder exams with flying colors. This has ignited many people’s interest in applying LLMs in more domains including EDA. However, the immediate future may not be as rosy as we might have thought.
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Driving Deterministic, Efficient Execution with Continuous Integration Flows
Resource (Slides) - Jun 14, 2023 by Kevin Campbell
Designer focused tools are proven solutions that help you detect issues as early as possible in the design cycle; reducing costs, and driving predictable schedule execution. Using these solutions in a continuous integration environment -- where design quality is checked at every code check in and at other scheduled intervals -- product teams improve efficiency across the board. Additionally, this directly helps designers and the consumers other their IP by improving the quality of their code.
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Functional Verification on Cloud: Opportunity and Challenge
Resource (Slides) - Jun 14, 2023 by David Lidrbauch
Cloud's dramatic growth is driven by hopes for better throughput, easier workload management, and lower costs. However, you may be asking yourself, " Really? Can renting compute and data storage be a better value than my on-premises data center? ” We will share some of our insights gained working with verification teams to scale projects to many 10's of thousands of simulations run on cloud.
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Formal Model Checking Made Easy
Resource (Slides) - Jun 14, 2023 by Martin Rowe
In this session anyone who is familiar with VHDL, Verilog, or SystemVerilog, and general verification practices, can learn the basics of formal. You will learn the basics of properties, how you can apply property checking to finding difficult corner case bugs, and easy-to-follow steps for verifying interfaces and other common design structures, as well as general design exploration.
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Continuous Integration (CI) / DevSecOps
Resource (Slides) - Jun 14, 2023 by Martin Rowe
Siemens' OneSpin Trust and Security tools and apps have technologies built upon world-class formal engines, and provide quantitative data verification results desired in emerging cybersecurity standards. In this presentation we will introduce apps that provide an automated assessment platform, perform processor verification, and offer completeness checking to perform security verification in your IC.
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When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered
Resource (Slides) - Jun 14, 2023 by Tom Fitzpatrick
You may have been told many different things about what AI/ML can do in the area of functional verification, but this presentation will give you the real story. Beginning with an overview of what AI/ML actually means and what is actually available today, we will share how we are incorporating this exciting technology across our product portfolio.
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Using Formal Technology for Secure IP Integration
Resource (Slides) - Jun 14, 2023 by John Hallman