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Don't Let VHDL Debugging Slow You Down! Use Questa One Sim
Resource (Slides (.PDF)) - Nov 12, 2025 Nicole Munson
In this webinar, you will learn how Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity.
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Introducing BUGGED OUT — A new bite-sized podcast for verification engineers
Resource (Verification Horizons Blog) - Nov 10, 2025 Harry Foster
I’m excited to share something I’ve been working on for a while — my new podcast, BUGGED OUT . If you’ve been in verification long enough, you know the truth: Every chip has bugs. The real challenge — and the real creativity — is in how we find and fix them quickly. This podcast is about that work. Each episode is 10–15 minutes, designed for a commute, a coffee break, or that moment when your simulation farm is spinning and you finally have a minute to think.
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HLV: Formal Verification of Synthesizable C++/SystemC Designs
Webinar - Nov 05, 2025 Vlada Kalinic
Formal check tools are difficult to be analyzed on generated RTL (as the errors cannot be correlated to HLS source code) Catapult Formal/Onespin SystemC help to overcome this challenge. Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.
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HLV: Formal Verification of Synthesizable C++/SystemC Designs
Resource (Slides (.PDF)) - Nov 05, 2025 Vlada Kalinic
Under HLV there are several apps, to verify and clean C++ HLS code before running HL Synthesis and then apply equivalency between C++ and RTL to guarantee that golden C++ is equivalent with final RTL design.
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BUGGED OUT Podcast - Episode 2: Jake Wiltgen
Resource (Podcast) - Oct 28, 2025 Harry Foster
Harry Foster talks with Jacob Wiltgen, Director of IC Verification Solutions at Siemens EDA, about insights from his white paper Accelerating DFT Sign-off with Questa One . They explore why Design-for-Test is more critical than ever, how DFT sign-off bottlenecks can be relieved, and what mega-trends like scaling, reliability, and in-system test mean for the future of verification.
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BUGGED OUT Podcast - Episode 1: Tom Fitzpatrick
Resource (Podcast) - Oct 28, 2025 Harry Foster
Harry Foster sits down with Tom Fitzpatrick to discuss insights from his white paper Better Stimulus Generation Through AI . Learn how Portable Stimulus and Questa One’s AI-driven assist are helping engineers overcome UVM’s limits, boost reuse, and accelerate verification productivity.
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Improving Verification Productivity Using Questa One Sim
Resource (Slides (.PDF)) - Oct 23, 2025 Karim Ameziane
This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim.
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Improving Verification Productivity Using Questa One Sim
Webinar - Oct 23, 2025 Karim Ameziane
This webinar is essential for verification engineers and managers looking to overcome the challenges of increasing design complexity and achieve superior verification efficiency and faster time-to-market with Siemens' Questa One Sim. Furthermore, the webinar will showcase Questa One Sim's cutting-edge debugging tools. Experience how advanced capabilities like Protocol Debug, and X-Debug enhance productivity, enabling you to find bugs faster.
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Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Resource (Recording) - Oct 16, 2025 Zvi Ben Yosef - NextSilicon
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Boosting Verification of an IEEE Compliant FPU with Formal and AI Capabilities
Resource (Slides (.PDF)) - Oct 16, 2025 Zvi Ben Yosef - NextSilicon
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Combining Performance and Formal Security Guarantees for Hardware Accelerators
Resource (Slides (.PDF)) - Oct 16, 2025 Lucas Deutschmann - RPTU University Kaiserslautern-Landau
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Combining Performance and Formal Security Guarantees for Hardware Accelerators
Resource (Recording) - Oct 16, 2025 Lucas Deutschmann - RPTU University Kaiserslautern-Landau
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New RTL Modeling Constructs in Verilog
Resource (Verification Horizons Blog) - Oct 16, 2025 Dave Rich
I’ve been packing up my office as Siemens is closing my location. This marks the longest I’ve ever spent in a single office, a whopping 15 years. Coincidentally, I was in the same building earlier with another company, Avant! for an additional 2 years. I’ve got a box of stuff from previous jobs that I rarely unpack. But it happened to go through it and found the proceedings from what was to become the first DVCon in 1992. I doubt these proceedings exist anywhere in digital form.
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Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Resource (Slides (.PDF)) - Oct 16, 2025 Tobias Ludwig - Lubis EDA
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Ground Truth in the Age of AI: Abstract Models as the Anchor of Verification
Resource (Recording) - Oct 16, 2025 Tobias Ludwig - Lubis EDA
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Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Resource (Recording) - Oct 16, 2025 Bryan Olmos - Infineon
The increasing shift towards the RISC-V open-source instruction set architecture requires the development of new design techniques. In recent years, it has been demonstrated that RISC-V designs can be generated in a modular and scalable manner by utilizing metamodeling techniques.
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Adaptable FWHW Formal Co-Verification of SoC RISC-V Components
Resource (Slides (.PDF)) - Oct 16, 2025 Bryan Olmos - Infineon
The increasing shift towards the RISC-V open-source instruction set architecture requires the development of new design techniques. In recent years, it has been demonstrated that RISC-V designs can be generated in a modular and scalable manner by utilizing metamodeling techniques.
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Formally Verifying Security Properties of CHERI Hardware and Software
Resource (Recording) - Oct 16, 2025 Thomas Bauereiss - University of Cambridge
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Formally Verifying Security Properties of CHERI Hardware and Software
Resource (Slides (.PDF)) - Oct 16, 2025 Thomas Bauereiss - University of Cambridge
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Harnessing AI for Real-world Hardware Verification
Resource (Slides (.PDF)) - Oct 16, 2025 Matthew Taylor - Doulos
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Harnessing AI for Real-world Hardware Verification
Resource (Recording) - Oct 16, 2025 Matthew Taylor - Doulos
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Stimulus Free Verification of a Clock Bridge Using Static and Formal
Resource (Recording) - Oct 16, 2025 Kanthi Palaniappan - Nokia
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Stimulus Free Verification of a Clock Bridge Using Static and Formal
Resource (Slides (.PDF)) - Oct 16, 2025 Kanthi Palaniappan - Nokia
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osmosis Europe 2025
Conference - Oct 16, 2025 Nicolae Tusinschi
The osmosis Europe event is a dynamic platform for exchanging successes achieved through applying formal techniques to overcome verification challenges. It offers a unique opportunity to connect and engage with our accomplished research and development (R&D) experts and participants. The conversations that follow may help you and others improve formal-based verification solutions.
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Ultra Accelerator Link (UALink) Verification: A Deep Dive with Siemens Avery Verification IP
Webinar - Oct 15, 2025 Justin Bunnell
In this webinar, you will be introduced to the UALink protocol, focusing on its architecture, key features that enable scalable AI systems, and critical verification challenges. We will then explore the essential capabilities of Siemens Avery UALink Verification IP, designed to ensure complete and efficient verification of complex UALink-based accelerator designs.