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Combined formal and functional verification approach for digitally controlled analog frontend
Resource (Slides) - Nov 16, 2023 by Mihajlo Katona - Veriest
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Limits of verification: learnings from catastrophic system failures
Resource (Recording) - Nov 16, 2023 by Philippe Luc
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How formal methods could banish the ghosts that haunt our computing systems
Resource (Slides) - Nov 16, 2023 by Prof. Wolfgang Kunz - RPTU
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Prof. Wolfgang Kunz - RPTU & Tobias Ludwig - Lubis EDA
Resource (Interview) - Nov 16, 2023 by Prof. Wolfgang Kunz of RPTU and Tobias Ludwig of Lubis EDA
Presenters Prof. Wolfgang Kunz of RPTU and Tobias Ludwig of Lubis EDA on future trends and applications of formal verification.
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Hierarchical verification flow for FPGA design projects
Resource (Recording) - Nov 16, 2023 by Mamma Benmoussa Garsault - Arcys
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How to sign-off cryptographic hash implementations with generated formal assertions
Resource (Recording) - Nov 16, 2023 by Tobias Ludwig - Lubis EDA
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Debugging enhancements for formal property checking
Resource (Recording) - Nov 16, 2023 by Holger Busch - Infineon
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osmosis 2023
Conference - Nov 16, 2023 by Nicolae Tusinschi
osmosis is about sharing success in using formal techniques to solve verification challenges, and networking with our R&D experts and other attendees.
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Prevent Performance Problems with Prompt RTL Profiling
Webinar - Nov 09, 2023 by Rich Edelman
Code profiling is a technique to identify performance issues in software code, helping developers understand how code is being executed, and identifying inefficient “hot spots” that are disproportionately impacting the code’s wall-clock run-time and memory usage.
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Smart Verification, Faster is not enough!
Resource (Slides) - Oct 30, 2023 by Harry Foster
Welcome to the dawn of EDA 4.0, a groundbreaking era marked by a profound revolution in electronic design automation, all propelled by the incredible capabilities of artificial intelligence. In this presentation, we'll embark on a captivating journey through the technological ages, beginning with the era of electrification and culminating in the era of cognification.
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Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations
Resource (Slides) - Oct 30, 2023 by Bob Oden
ASIC’s and FPGA’s increasingly include DSP, algorithm, AI, and ML blocks created using MATLAB or Simulink. Simulating these blocks within the context of adjacent RTL is required for verifying integration and system performance. Cooperation between Mathworks and Siemens has produced an automated flow for verifying these blocks within subsystem and full chip UVM based simulation environments.
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When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered
Resource (Slides) - Oct 30, 2023 by Tom Fitzpatrick
You may have been told many different things about what AI/ML can do in the area of functional verification, but this presentation will give you the real story. Beginning with an overview of what AI/ML actually means and what technology is actually available today, we’ll explore many of the ways that we’re incorporating this exciting technology across our product portfolio.
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Industry Trends in Functional Verification!
Resource (Slides) - Oct 30, 2023 by Harry Foster
This talk unveils the outcomes of a comprehensive two-decade-long double-blind industry study focusing on the functional verification of Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) designs, with a focus on the aerospace and defense markets. The insights derived from this extensive research shed light on a myriad of pressing challenges, notably the growing prevalence of bug escapes into production and the persistent issue of missed project schedules.
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Success with Continuous Integration and Continuous Development (CI/CD) Pipeline using automated checking
Resource (Slides) - Oct 30, 2023 by Afzal Usmani - Siemens EDA
Mistakes happen, but finding and fixing issues late in programs increases overall program scope, as well as schedule and resource requirements. Competitive pressures push teams constantly to do more. Functional verification teams face significant challenges to build testbenches quickly, uncover design issues and enable rapid debug. Incomplete or incorrect bug fixes (or even a hurried introduction of new bugs) compound the problem.
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MARLUG - 2023
Seminar - Oct 30, 2023 by Harry Foster
User2User Mid-Atlantic is your opportunity to learn, grow and connect with fellow technical experts who design leading-edge products using Siemens EDA tools.
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Selective hardening in space applications
Resource (Verification Horizons Blog) - Oct 24, 2023 by Jacob Wiltgen
The space sector continues to experience disruption as innovation drives the creation of new business models across government and commercial entities. Low Earth Orbit (LEO) constellations, Traffic and Management applications, and advanced communication systems are just a few examples where innovation is driving the next generation of semiconductor development targeted for space based applications.
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Starting Your UVM Simulation
Resource (Verification Horizons Blog) - Oct 10, 2023 by Chris Spear
What happens when you start your simulation with a UVM testbench? Where should you put the uvm_config_db::set() calls to send the virtual interface to the test class? Are there potential race conditions? And what happens when your test is over?
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Selective Radiation Mitigation for Integrated Circuits
Paper - Oct 09, 2023 by Jacob Wiltgen
Shortened lifecycles and cost reduction coupled with the demand for advanced capabilities continue to challenge project teams delivering IC into space systems. To meet these demands, project teams continue evolving across all aspects of the lifecycle, including the implementation and verification of mitigation protections against single event effects. This paper defines a methodology that enables teams to perform selective radiation mitigation and implement an optimal mitigation architecture.
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Selective Radiation Mitigation for Integrated Circuits
Resource (Technical Paper) - Oct 09, 2023 by Jacob Wiltgen
This paper defines a methodology that enables teams to perform selective radiation mitigation and implement an optimal mitigation architecture.
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Questa Formal Apps Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Even the most carefully designed testbench is inherently incomplete since constrained-random methods cannot hit every corner case. Unfortunately, even after 100% functional coverage is achieved there can still be showstopper bugs hiding in unimagined state spaces. Questa Formal Apps statically analyze a design’s behavior with respect to a given set of properties; then exhaustively explore all possible input sequences in a breadth-first search manner.
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Questa Verification IQ Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Big data is transforming all industries, enabling them to innovate their products more rapidly and improve many aspects of our lives. EDA is powering these transformations. Verification needs to transform in step, so we can predict which test to run next, the root cause of a failure, and what stimulus is required. Questa Verification IQ is the Siemens EDA collaborative, data-driven verification solution that transforms the verification process using analytics, collaboration, and traceability.
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Questa RDC Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa RDC identifies reset domains, the related clock domains, and reset domain synchronizers, as well as low power structures via the Unified Power Format (UPF). The technology then exhaustively checks for any potential RDC errors, statically verifying that all signals crossing asynchronous reset and clock domain boundaries are guarded by RDC synchronizers. Any discovered issues are illustrated using familiar schematic and waveform displays.
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Questa Lint Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
Questa Lint provides actionable results with low noise. Questa Lint reviews reported issues, then uses its deep understanding of every issue known to provide results different than inferred intent (as well as those known to cause false violations), to adapt the results. This results in Questa Lint reporting only the issues that need to be fixed, and in the order of those that matter most, resulting in actionable results and faster fix cycles.
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Austemper Analysis and Fault Simulation
Resource (Fact Sheet) - Oct 01, 2023 by
The Austemper closed-loop safety flow analyzes and validates the resilience of mission-critical designs to mitigate random faults. Early, accurate safety analysis with automatic identification of where to add safety enhancements, combined with fast fault simulation provides an efficient closed-loop safety flow for the development of automotive ICs.
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QuestaSim Fact Sheet
Resource (Fact Sheet) - Oct 01, 2023 by
The QuestaSim™ verification solution from Siemens EDA, a part of Siemens Digital Industries Software, continues to evolve in response to the growing complexity of SoC designs. In addition to the sheer size of designs and the inclusion of multiple embedded processors and advanced interconnect systems, the increase in software content and the configurability required by multi-platform design requires a functional verification solution that unifies a broad arsenal of verification features.